IP Library Granted Patent US 12690197
Granted Patent B2
US 12690197 · App. 17/546,255 · Granted Jul 21, 2026

Memory cell, memory device, and methods thereof

Inventor: Stefan Ferdinand Müller (Radebeul, DE)
Assignee: Ferroelectric Memory GmbH
H10B53/30
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Quick Facts
Patent No.
US 12690197
App. No.
17/546,255
Granted
Jul 21, 2026
Kind
B2
Abstract

Various aspects relate to a memory cell, the memory cell including: a field-effect transistor structure; and a capacitive memory structure; wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider; wherein the capacitive memory structure includes: a first electrode layer, a second electrode layer, and a memory element structured to have at least a first region extending from the first electrode layer to the second electrode layer and a second region extending from the first electrode layer to the second electrode layer, wherein the first region consists of a first material, wherein the second region consists of a second material, and wherein the first material is different from the second material.

Claims (43)

1 . A memory cell comprising:

a field-effect transistor structure; and

a capacitive memory structure;

wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider;

wherein the capacitive memory structure comprises:

a first electrode,

a second electrode, and

a memory element structured to have at least a first region extending from the first electrode to the second electrode and a second region extending from the first electrode to the second electrode,

wherein the first region consists of a first material comprising a spontaneously-polarizable material,

wherein the second region consists of a second material substantially free of a spontaneously-polarizable material.

2 . The memory cell according to claim 1 ,

wherein the first material comprises a base material having a first concentration of dopant elements,

wherein the second material comprises the base material having a second concentration of dopant elements different from the first concentration of dopant elements or wherein the second material comprises the base material having substantially no dopant elements.

3 . The memory cell according to claim 1 ,

wherein the first region comprises at least a single grain of a spontaneously-polarizable material that is in contact with both the first electrode and the second electrode, and

wherein the second region is free of a single grain of a spontaneously-polarizable material that is in contact with both the first electrode and the second electrode.

4 . The memory cell according to claim 1 ,

wherein the first region comprises a first metal oxide,

wherein the second region comprises a second metal oxide, and

wherein the first metal oxide differs from the second metal oxide in at least one of chemical composition and/or crystal structure.

5 . The memory cell according to claim 1 ,

wherein an actual depolarization field value associated with the capacitive memory structure is defined by polarization characteristics of the first region and the second region, and

wherein the actual depolarization field value is less than a depolarization field value associated with the first region defined by a material-specific polarization characteristic of the first material.

6 . The memory cell according to claim 1 ,

wherein the first region has a width less than a width of the first electrode and less than a width of the second electrode.

7 . The memory cell according to claim 1 ,

wherein the memory element further comprises a separation structure disposed between the first region and the second region.

8 . The memory cell according to claim 1 ,

wherein the first region directly contacts each of the first electrode and the second electrode, and

wherein the second region directly contacts each of the first electrode and the second electrode.

9 . The memory cell according to claim 1 , wherein the capacitive memory structure is stacked directly over a gate of the field-effect transistor structure.

10 . A memory cell comprising:

a field-effect transistor structure; and

a capacitive memory structure integrated into the field-effect transistor structure;

wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider;

wherein the capacitive memory structure comprises:

a top layer comprising one or more electrode layers,

a bottom isolation layer, and

a memory element structured to have at least a first region extending from the top layer to the bottom isolation layer and a second region extending from the top layer to the bottom isolation layer,

wherein the first region consists of a first material,

wherein the second region consists of a second material, and

wherein the first material is different from the second material.

11 . The memory cell according to claim 10 , wherein the first material comprises a spontaneously-polarizable material, and wherein the second material is substantially free of a spontaneously-polarizable material.