IP Library Granted Patent US 12690210
Granted Patent B2
US 12690210 · App. 18/360,045 · Granted Jul 21, 2026

Manufacturing method for semiconductor device

Inventors: Kakeru Otsuka (Tokyo, JP); Hayato Okamoto (Tokyo, JP); Katsumi Nakamura (Tokyo, JP); Koji Tanaka (Tokyo, JP); Koichi Nishi (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H10D12/481H10D12/038H10D84/403
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690210
App. No.
18/360,045
Granted
Jul 21, 2026
Kind
B2
Abstract

A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer includes a complex defect of interstice carbon and interstice oxygen having density decreasing from the second principal plane side toward the first principal plane side.

Claims (23)

1 . A manufacturing method for a semiconductor device comprising:

preparing a semiconductor substrate of a first conduction type having a first principal plane and a second principal plane opposed to the first principal plane and having carbon and oxygen;

forming a first semiconductor layer of a second conduction type having impurity concentration higher than impurity concentration of the semiconductor substrate on the first principal plane side of the semiconductor substrate;

after forming the first semiconductor layer, grinding the semiconductor substrate from the second principal plane side;

after grinding the semiconductor substrate, forming a second semiconductor layer of the first conduction type or the second conduction type having impurity concentration higher than impurity concentration of the semiconductor substrate on the second principal plane side of the semiconductor substrate;

after grinding the semiconductor substrate, injecting protons from the second principal plane side;

a first heat treatment step of heating the semiconductor substrate at a first temperature, converting the protons injected into the semiconductor substrate into hydrogen-induced donors, and forming a first buffer layer of the first conduction type having impurity concentration higher than the impurity concentration of the semiconductor substrate;

after the first heat treatment step, a charged particle irradiating step of irradiating the semiconductor substrate with charged particles and forming a complex defect of interstice carbon and interstice oxygen and a complex defect of interstice carbon and lattice position carbon; and

after the charged particle irradiating step, a second heat treatment step of heating the semiconductor substrate at a second temperature lower than the first temperature and extinguishing the complex defect of interstice carbon and lattice position carbon.

2 . The manufacturing method for a semiconductor device according to claim 1 , wherein the complex defect of interstice carbon and lattice position carbon is extinguished more than the complex defect of interstice carbon and interstice oxygen in the second heat treatment step.

3 . The manufacturing method for a semiconductor device according to claim 1 , wherein the charged particles are electrons or protons.

4 . The manufacturing method for a semiconductor device according to claim 1 , wherein the complex defect of interstice carbon and interstice oxygen is a lifetime killer which reduces a recombination life time of a carrier.

5 . The manufacturing method for a semiconductor device according to claim 1 , wherein the complex defect of interstice carbon and interstice oxygen is formed in the first buffer layer.

6 . The manufacturing method for a semiconductor device according to claim 1 , wherein the first temperature is 380° C. or higher and 525° C. or lower, and

the second temperature is 250° C. or higher and 350° C. or lower.

7 . The manufacturing method for a semiconductor device according to claim 1 , wherein the step of forming the second semiconductor layer includes, after injecting an impurity of the first conduction type or an impurity of the second conduction type from the second principal plane side of the semiconductor substrate, irradiating the second principal plane of the semiconductor substrate with laser beam in air, and

the charged particle irradiating step is performed after forming the second semiconductor layer.

8 . The manufacturing method for a semiconductor device according to claim 1 , further comprising forming a second buffer layer of the first conduction type having phosphorus as impurities and having impurity concentration higher than impurity concentration of the first buffer layer between the second semiconductor layer and the first buffer layer,

wherein the charged particle irradiating step is performed after forming the second buffer layer.

9 . The manufacturing method for a semiconductor device according to claim 1 , comprising a film forming step of forming a metal film on the second semiconductor layer, and a sinter treatment step of heating the metal film,

wherein the film forming step is performed between the first heat treatment step and the second heat treatment step, and

the sinter treatment step is performed by the second heat treatment step.

10 . The manufacturing method for a semiconductor device according to claim 9 , wherein the film forming step includes a step of sputtering or vapor-depositing a metal layer including at least one of Al, Ti, Ni, Au, Ag, and Cu on the second semiconductor layer.