Semiconductor optoelectronic integrated circuit and methodology for making same employing gate-all-around epitaxial structures
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include a p-type gate-all-around layer structure that includes a plurality of quantum well structures formed between a pair of p-type thin doped layers spaced vertically from one another. A p-type layer is formed above the p-type gate-all-around layer structure. An etch operation exposes the p-type layer. P-type ions are implanted into the exposed second p-type layer to a depth that extends through the p-type gate-all-around layer structure and contacts the p-type thin doped layers of the p-type gate-all-around layer structure. A gate electrode of an n-channel HFET device is formed in contact with the ion-implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with ion-implanted n-type regions that contact the plurality of quantum well structures of the p-type gate-all-around layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.
1 . A method of forming an integrated circuit comprising:
depositing or providing a plurality of semiconductor layers supported on a substrate, wherein the plurality of semiconductor layers include a p-type gate-all-around layer structure that includes a plurality of quantum well structures formed between a pair of p-type thin doped layers spaced vertically from each other;
implanting p-type ions into the plurality of semiconductor layers to form at least one ion-implanted p-type gate contact region that extends through the p-type gate-all-around layer structure and contacts the p-type thin doped layers of the p-type gate-all-around layer structure;
implanting n-type ions into the plurality of semiconductor layers to form an ion-implanted n-type source contact region and an ion-implanted n-type drain contact region, both of which are in contact with the p-type gate-all-around layer structure;
forming a gate electrode of an n-channel heterojunction field effect transistor (HFET) device in contact with the at least one ion-implanted p-type gate contact region; and
forming source and drain electrodes of the n-channel HFET device in contact with the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively.
2 . The method according to claim 1 , wherein:
the plurality of semiconductor layers further includes a non-inverted n-type modulation-doped quantum well structure formed below the p-type gate-all-around layer structure, wherein the non-inverted n-type modulation-doped quantum well structure includes an n-type charge sheet disposed above at least one pair of quantum well layer and barrier layer.
3 . The method according to claim 2 , wherein:
the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region are both in contact with the non-inverted n-type modulation-doped quantum well structure.
4 . The method according to claim 1 , wherein:
the plurality of semiconductor layers further includes at least one additional layer formed above the p-type gate-all-around layer structure;
an etch operation (E1) is performed into the plurality of semiconductor layers, wherein the etch operation (E1) exposes a portion of the at least one additional layer; and
p-type ions are implanted into the plurality of semiconductor layers through the portion of the at least one additional layer exposed by the etch operation (E1) to form the at least one ion-implanted p-type gate contact region.
5 . The method according to claim 1 , wherein:
the plurality of quantum well structures of the p-type gate-all-around layer structure comprises a non-inverted n-type modulation-doped quantum well structure disposed above an inverted n-type modulation-doped quantum well structure, wherein the non-inverted n-type modulation-doped quantum well structure includes an n-type charge sheet disposed above at least one pair of quantum well layer and barrier layer, and wherein the inverted n-type modulation-doped quantum well structure includes at least one pair of quantum well layer and barrier layer disposed above the n-type charge sheet.
6 . The method according to claim 1 , further comprising:
performing thermal anneal operations that anneal the at least one ion-implanted p-type gate contact region, the ion-implanted n-type source contact region, and the ion-implanted n-type drain contact region before forming the gate electrode and the source and drain electrodes of the n-channel HFET device.
7 . The method according to claim 1 , further comprising:
forming a feature from a refractory metal, wherein the feature overlies a quantum well channel region provided by the p-type gate-all-around layer structure, wherein the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region are disposed opposite one another along opposite sides of the feature, and the at least one ion-implanted p-type gate contact region is disposed adjacent at least one end of the feature.
8 . The method according to claim 1 , wherein:
the plurality of semiconductor layers further includes an n-type gate-all-around layer structure that includes at least one quantum well structure formed between a pair of n-type thin doped layers spaced vertically from one another, wherein at least one spacer layer is disposed between the p-gate-all-around layer structure and the n-type gate-all-around layer structure.
9 . The method according to claim 8 , further comprising:
implanting n-type ions into the plurality of semiconductor layers to form at least one ion-implanted n-type gate contact region that extends through the n-type gate-all-around layer structure and contacts the n-type thin doped layers of the n-type gate-all-around layer structure;
implanting p-type ions into the plurality of semiconductor layers to form an ion-implanted p-type source contact region and an ion-implanted p-type drain contact region, both of which are in contact with the n-type gate-all-around layer structure;
forming a gate electrode of a p-channel heterojunction field effect transistor (HFET) device in contact with the at least one ion-implanted n-type gate contact region; and
forming source and drain electrodes of the p-channel HFET device in contact with the ion-implanted n-type source contact region and the ion-implanted n-type drain contact region, respectively.
10 . The method according to claim 9 , wherein:
the plurality of semiconductor layers further includes an inverted p-type modulation-doped quantum well structure formed above the n-type gate-all-around layer structure, wherein the inverted p-type modulation-doped quantum well structure includes at least one pair of quantum well layer and barrier layer disposed above a p-type charge sheet by the at least one spacer layer.
11 . The method according to claim 10 , wherein:
the ion-implanted p-type source contact region and the ion-implanted n-type drain contact region are both in contact with the inverted p-type modulation-doped quantum well structure.
12 . The method according to claim 9 , further comprising:
performing an etch operation (E2) into the plurality of semiconductor layers, wherein the etch operation (E2) exposes a portion of the at least one spacer layer;
wherein the n-type ions are implanted into the plurality of semiconductor layers through the portion of the at least one spacer layer exposed by the etch operation (E2) to form the at least one ion-implanted n-type gate contact region.
13 . The method according to claim 8 , wherein:
the at least one quantum well structure of the n-type gate-all-around layer structure comprises a non-inverted p-type modulation-doped quantum well structure disposed above an inverted p-type modulation-doped quantum well structure, wherein the non-inverted p-type modulation-doped quantum well structure includes a p-type charge sheet disposed above at least one pair of quantum well layer and barrier layer, and wherein the inverted p-type modulation-doped quantum well structure includes at least one pair of quantum well layer and barrier layer disposed above the p-type charge sheet.
14 . The method according to claim 9 , further comprising:
performing thermal anneal operations that anneal the at least one ion-implanted n-type gate contact region, the ion-implanted p-type source contact region, and the ion-implanted p-type drain contact region before forming the gate electrode and the source and drain electrodes of the p-channel HFET device.
15 . The method according to claim 9 , further comprising:
forming an additional feature from a refractory metal, wherein the additional feature overlies a quantum well channel region provided by the n-type gate-all-around layer structure, wherein the ion-implanted p-type source contact region and the ion-implanted p-type drain contact region are disposed opposite each other along opposite sides of the additional feature, and the at least one ion-implanted n-type gate contact region is disposed adjacent at least one end of the additional feature.
16 . The method according to claim 10 , wherein:
the plurality of semiconductor layers further includes a non-inverted n-type modulation-doped quantum well structure formed below the p-type gate-all-around layer structure, wherein the non-inverted n-type modulation-doped quantum well structure includes an n-type charge sheet disposed above at least one pair of quantum well layer and barrier layer.
17 . The method according to claim 1 , further comprising:
while forming the n-channel HFET device, forming at least one optoelectronic device or optical device as part of the integrated circuit;
wherein the at least one optoelectronic device or optical device optionally has PIN diode-like current-voltage characteristics; and
wherein the at least one optoelectronic device or optical device optionally has thyristor-like current-voltage characteristics.
18 . The method according to claim 1 , wherein:
the plurality of semiconductor layers comprises III-V compound semiconductor materials, such as gallium arsenide semiconductor materials.