FinFETs with low source/drain contact resistance
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
1 . A method comprising:
forming a fin structure extending from a substrate;
depositing a dielectric layer over the fin structure, leaving a top portion of the fin structure exposed above a top surface of the dielectric layer;
forming a gate structure extending over the fin structure;
recessing a portion of the fin structure to form a recess, wherein the dielectric layer forms a sidewall of the recess on at least two sides;
epitaxially growing a source/drain region in the recess, wherein growth of the source/drain region is constrained by the dielectric layer sidewalls to form a columnar source/drain region when viewed in cross-section;
continuing the epitaxial growth of the source/drain region to extend above a top surface of the dielectric layer, wherein the source/drain region extends laterally over the top surface of the dielectric layer to form a faceted region when viewed in cross-section;
forming a source/drain contact contacting outer sides of the faceted region of the source/drain region and at least a portion of the columnar region of the source/drain region; and
depositing an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contact.
2 . The method of claim 1 , wherein the step of recessing a portion of the fin structure includes recessing portions of the fin structure, on respective sides of the gate structure, to below a top surface of the dielectric layer.
3 . The method of claim 1 , further comprising recessing a portion of the dielectric layer to form a recessed surface of the dielectric layer, such that a topmost surface of the fin structure extends higher than the recessed surface of the dielectric layer.
4 . The method of claim 1 , further comprising depositing a buffer oxide layer over the source/drain region before forming the ILD.
5 . The method of claim 4 , further comprising depositing a contact etch stop layer (CESL) over the buffer oxide layer before forming the ILD.
6 . The method of claim 5 , wherein the step of depositing a buffer oxide layer includes depositing silicon oxide by atomic layer deposition.
7 . The method of claim 5 , wherein the step of depositing a CESL includes depositing a material selected from the group consisting of silicon nitride and silicon carbonitride by atomic layer deposition.
8 . The method of claim 1 , further comprising siliciding the source/drain region before the step of forming a source/drain contact.
9 . A method comprising:
forming a plurality of semiconductor fins extending from a substrate;
depositing an isolation layer around the semiconductor fins, the isolation layer having a portion with a top surface that extends between the lowest portions of the respective semiconductor fins;
epitaxially growing fin extensions on respective source and drain regions of the plurality of semiconductor fins, the fin extensions extending vertically and laterally beyond boundaries of the plurality of semiconductor fins, wherein respective fin extensions further extend lower than the top surface of the portion of the isolation layer;
siliciding outer portions of the fin extensions to form respective conductive liners; and
forming conductive contacts in contact with a respective top surface, underside, and sidewalls of the respective fin extensions.
10 . The method of claim 9 , wherein the respective fin extension include respective down-facing facets, and the step of siliciding outer portions of the fin extensions includes siliciding the respective down-facing facets.
11 . The method of claim 9 , further comprising forming one conductive contact that electrically contacts a plurality of fin extensions.
12 . The method of claim 9 , wherein the isolation layer further has a second to surface adjacent one of the semiconductor fins that is at a higher plane than the top surface that extends between the lowest portions of the respective semiconductor fins.
13 . The method of claim 9 , further comprising depositing the isolation layer to cover the fin extensions and forming a recess in the isolation layer to form the portion with a top surface that extends between the lowest portions of the respective semiconductor fins.
14 . The method of claim 13 , wherein a top surface of the isolation layer revealed after forming the recess is higher than a bottom surface of the respective fin extensions.
15 . The method of claim 9 , wherein the portion of the fin extensions extending vertically and laterally beyond boundaries of the plurality of semiconductor fins have respective diamond-shaped profiles when viewed in cross-section.
16 . A method comprising:
forming a semiconductor fin;
surrounding a lower portion of the semiconductor fin with an isolation layer, wherein an upper portion of the semiconductor fin extends over a top surface of the isolation layer;
forming a gate stack on a top surface and sidewalls of a first portion of the semiconductor fin;
etching a second portion of the semiconductor fin to form a recess, wherein opposite sidewalls of the recess are formed by portions of the isolation layer;
epitaxially growing a first portion of an epitaxy semiconductor region in a columnar shape between the sidewalls formed by portions of the isolation layer;
epitaxially growing a second portion of the epitaxy semiconductor region atop the first portion of the epitaxy semiconductor region, the second portion extending over the top surface of the isolation layer;
etching the isolation layer, to expose opposite sidewalls of the epitaxy semiconductor region; and
forming a contact plug electrically contacting the epitaxy semiconductor region.
17 . The method of claim 16 , further comprising siliciding the first portion and the second portion of the epitaxy semiconductor region.
18 . The method of claim 16 , wherein the step of surrounding a lower portion of the semiconductor fin with an isolation layer, wherein an upper portion of the semiconductor fin extends over a top surface of the isolation layer, includes covering the semiconductor fin with isolation layer and then recessing a portion of the isolation layer to form a recessed portion of the isolation layer.
19 . The method of claim 18 , wherein a top surface of the recessed portion of the isolation layer is below a bottom-most surface of the second portion of the epitaxy semiconductor region.
20 . The method of claim 16 , further comprising siliciding the first portion and the second portion of the epitaxy semiconductor region prior to the step of forming a contact plug.