Semiconductor device with spacer and C-shaped channel portion, method of manufacturing semiconductor device with spacer and C-shaped channel portion, and electronic apparatus
Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.
1 . A semiconductor device, comprising:
a channel portion on a substrate, wherein the channel portion comprises a curved nanosheet or nanowire with a C-shaped cross-section;
a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate;
a first gate stack and a second gate stack located on opposite sides of the channel portion, wherein each of the first gate stack and the second gate stack comprises a gate dielectric layer and a gate conductor layer;
a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and
a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively,
wherein an upper surface of the first spacer and an upper surface of the gate dielectric layer of the first gate stack are coplanar, and
wherein an upper surface of the second spacer and an upper surface of the gate dielectric layer of the second gate stack are coplanar.
2 . The semiconductor device according to claim 1 , wherein the first spacer and the second spacer have thicknesses different from each other.
3 . The semiconductor device according to claim 1 , wherein the first spacer and the second spacer comprise dielectrics different from each other.
4 . The semiconductor device according to claim 1 , wherein the first gate stack and the second gate stack form a gate stack surrounding an outer periphery of the channel portion.
5 . The semiconductor device according to claim 4 , wherein the first spacer and the second spacer form a spacer surrounding the outer periphery of the channel portion.
6 . The semiconductor device according to claim 5 , further comprising:
a third spacer and a fourth spacer on opposite sides of the channel portion in a first direction, wherein the first spacer and the second spacer are located on opposite sides in a second direction intersecting the first direction,
wherein the first spacer is respectively connected to the third spacer and the fourth spacer, and there is an interface at each of a connection position of the first spacer and the third spacer and a connection position of the first spacer and the fourth spacer; the second spacer is respectively connected to the third spacer and the fourth spacer, and there is an interface at each of a connection position of the second spacer and the third spacer and a connection position of the second spacer and the fourth spacer.
7 . The semiconductor device according to claim 6 , wherein portions of the first spacer, the second spacer, the third spacer, and the fourth spacer on the gate stack are coplanar, and portions of the first spacer, the second spacer, the third spacer, and the fourth spacer under the gate stack are coplanar.
8 . The semiconductor device according to claim 1 , wherein the first spacer and the second spacer are self-aligned with the upper and lower ends of the channel portion.
9 . The semiconductor device according to claim 1 , wherein the curved nanosheet or nanowire comprises a first sidewall and a second sidewall having a C-shaped opening towards a same direction in a cross-section perpendicular to a surface of the substrate, wherein the first sidewall and the second sidewall extend between the source/drain portions at the upper and lower ends of the channel portion, the first gate stack overlaps with the first sidewall, and the second gate stack overlaps with the second sidewall.
10 . The semiconductor device according to claim 9 , wherein the curved nanosheet or nanowire has a uniform thickness or diameter.
11 . The semiconductor device according to claim 1 , further comprising:
a vertically extending active layer, wherein the active layer comprises a middle portion extending between an upper portion and a lower portion of the active layer, and the middle portion of the active layer forms the curved nanosheet or nanowire;
a first semiconductor layer on a sidewall of the upper portion of the active layer; and
a second semiconductor layer on a sidewall of the lower portion of the active layer,
wherein the first source/drain portion and the second source/drain portion comprise a doping region in the first semiconductor layer and the second semiconductor layer.
12 . The semiconductor device according to claim 11 , wherein the first semiconductor layer extends from the sidewall of the upper portion of the active layer towards a side away from an opening of the C-shaped cross-section, and the second semiconductor layer extends from the sidewall of the upper portion of the active layer towards the side away from the opening of the C-shaped cross-section.
13 . The semiconductor device according to claim 1 , wherein at least a portion of each of the first gate stack and the second gate stack close to a side of the channel portion is coplanar with the channel portion.
14 . The semiconductor device according to claim 1 , wherein the channel portion and/or the source/drain portion contain a single crystal semiconductor material.
15 . The semiconductor device according to claim 1 , wherein there are a plurality of the semiconductor devices on the substrate, and the C-shaped cross-section of at least one pair of semiconductor devices among the plurality of the semiconductor devices face away from each other.
16 . The semiconductor device according to claim 1 , wherein a gate length of the first gate stack is equal to a gate length of the second gate stack.
17 . An electronic apparatus, comprising the semiconductor device according to claim 1 .
18 . The electronic apparatus according to claim 17 , wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, an automotive electronic device, a communication device, or an Internet of Things device.