Field effect transistor with gate isolation structure and method

1 . A device, comprising:

a first vertical stack of first nanostructures formed over a substrate;

a second vertical stack of second nanostructures adjacent to the first vertical stack;

a first gate structure adjacent the first nanostructures, the first gate structure including:

a first gate portion between the first nanostructures;

a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion, the second sidewall being between the first sidewall and the substrate, the second gate portion being a different material than the first gate portion;

an interfacial layer on the first nanostructures, wherein a thickness of the interfacial layer is thicker on horizontal end portions of the first nanostructures than on upper and lower surfaces of the first nanostructures; and

a gate dielectric layer on the interfacial layer;

a second gate structure adjacent the second nanostructures; and

a second wall structure between the second gate portion and the second gate structure.

2 . The device of claim 1 , wherein the second gate portion includes one or more of tungsten, titanium or platinum.

3 . The device of claim 1 , further comprising:

a conductive layer on the first gate portion and the second gate portion; and

a gate isolation structure that extends from an upper surface of the conductive layer to a level that is below an uppermost surface of the first gate structure.

4 . The device of claim 1 , wherein the thickness of the interfacial layer at the horizontal end portions is in a range of about 2 nanometers (nm) to about 3 nm.

5 . The device of claim 1 , wherein a thickness of the second gate portion adjacent vertical sidewalls of the first nanostructures is in a range of about 3 nm to about 10 nm.

6 . The device of claim 1 , wherein a width of the second wall structure is in a range of about 10 nm and about 100 nm.

7 . The device of claim 1 , further comprising:

a first source/drain region abutting the first vertical stack;

a second source/drain region abutting the second vertical stack; and

a first wall structure between the first source/drain region and the second source/drain region.

8 . The device of claim 7 , wherein a width of the first wall structure is in a range of about 20 nm to about 100 nm.

9 . A device, comprising:

a first nanostructure device, including:

a first semiconductor channel over a substrate;

a second semiconductor channel over the first semiconductor channel;

a first gate portion between the first and second semiconductor channels;

a second gate portion between the first and second semiconductor channels, and on vertical sidewalls of the first and second semiconductor channels; and

a first source/drain region abutting the first and second semiconductor channels;

first horizontal end portions of the first semiconductor channel and the second semiconductor channel; and

first upper surfaces and first lower surfaces of the first semiconductor channel and the second semiconductor channel;

a first interfacial layer on the first semiconductor channel and on the second semiconductor channel, wherein a first thickness of the interfacial layer is thicker on the first horizontal end portions of the first semiconductor channel and the second semiconductor channel than on the first upper surfaces and the first lower surfaces of the first semiconductor channel and the second semiconductor channel;

a first gate dielectric layer on the first interfacial layer;

a second nanostructure device adjacent the first nanostructure device, the second nanostructure device including:

a third semiconductor channel;

a fourth semiconductor channel over the third semiconductor channel;

a third gate portion between the third and fourth semiconductor channels;

a fourth gate portion between the third and fourth semiconductor channels, and on vertical sidewalls of the third and fourth semiconductor channels;

a second source/drain region abutting the third and fourth semiconductor channels;

second horizontal end portions of the third semiconductor channel and the fourth semiconductor channel; and

second upper surfaces and second lower surfaces of the third semiconductor channel and the fourth semiconductor channel;

a second interfacial layer on the third semiconductor channel and on the fourth semiconductor channel, wherein a second thickness of the interfacial layer is thicker on the second horizontal end portions of the third semiconductor channel and the fourth semiconductor channel than on the second upper surfaces and the second lower surfaces of the third semiconductor channel and the fourth semiconductor channel;

a second gate dielectric layer on the second interfacial layer;

a first wall structure between the first and second source/drain regions; and

a second wall structure between the second gate portion and the fourth gate portion.

10 . The device of claim 9 , wherein an upper surface of the second wall structure is at a level substantially coplanar with an upper surface of the fourth gate portion.

11 . The device of claim 9 , wherein an upper surface of the second wall structure is at a level lower than an upper surface of the fourth gate portion.

12 . The device of claim 9 , further comprising:

a conductive layer on the second gate portion and the fourth gate portion; and

a gate isolation structure extending from an upper surface of the conductive layer to an upper surface of the second wall structure.

13 . The device of claim 12 , wherein a width of the gate isolation structure is larger than width of the second wall structure.

14 . The device of claim 9 , wherein the first thickness of the first interfacial layer is in a range of about 2 nanometers to about 3 nanometers.

15 . The device of claim 14 , wherein the second thickness of the second interfacial layer is in a range of about 2 nanometers to about 3 nanometers.

16 . A device, comprising:

a first vertical stack of semiconductor channels over a substrate;

a second vertical stack of semiconductor channels adjacent to the first vertical stack;

a first gate structure adjacent the first vertical stack, the first gate structure including:

an interfacial layer on the channels having a first thickness on upper and lower surfaces of the channels and a second thickness on horizontal end portions of the channels that is greater than the first thickness;

a gate dielectric on the interfacial layer;

a first gate portion between vertically adjacent ones of the channels, and a second gate portion of a material different from the first gate portion on vertical sidewalls of the channels and connecting the first gate portion across the horizontal end portions;

a second gate structure adjacent the second vertical stack and including:

a third gate portion between vertically adjacent ones of the channels of the second vertical stack;

a fourth gate portion on vertical sidewalls of the channels of the second vertical stack; and

a dielectric wall structure disposed between the second and fourth gate portions.

17 . The device of claim 16 , wherein the interfacial layer at the horizontal end portions has a thickness in a range of about 2 nanometers to about 3 nanometers.

18 . The device of claim 16 , wherein the dielectric wall structure has a width in a range of about 10 nanometers to about 100 nanometers.

19 . The device of claim 16 , further comprising a conductive layer on the first and second gate portions and on the third and fourth gate portions.

20 . The device of claim 19 , further comprising a gate isolation structure extending from an upper surface of the conductive layer to an upper surface of the wall structure.