Semiconductor structures and manufacturing methods thereof
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located on a source region and a drain region of the etch stop layer.
1 . A semiconductor structure, comprising:
a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer sequentially arranged from a bottom of the semiconductor structure to a top of the semiconductor structure, wherein a two-dimensional hole gas is formed at an interface between the back barrier layer and the channel layer, the etch stop layer is vertically above the two-dimensional hole gas; and
a P-type semiconductor layer located in a source region and a drain region on the etch stop layer, wherein a P-type ion heavily doped layer is provided on the P-type semiconductor layer in the source region and the P-type semiconductor layer in the drain region.
2 . The semiconductor structure of claim 1 , wherein a material of the P-type semiconductor layer comprises a group III nitride material.
3 . The semiconductor structure of claim 1 , wherein a material of the etch stop layer comprises at least one of: AlN, AlGaN, an alternating multilayer superlattice structure with GaN/AlGaN, or an alternating multilayer superlattice with AlGaN/AlN.
4 . The semiconductor structure of claim 1 , wherein the etch stop layer includes a P-type doped material.
5 . The semiconductor structure of claim 1 , wherein the channel layer-comprises a group III nitride material.
6 . The semiconductor structure of claim 1 , wherein a source electrode is provided on the P-type semiconductor layer in the source region, and a drain electrode is provided on the P-type semiconductor layer in the drain region, a multi-layer structure, comprising a gate electrode insulating layer and a gate electrode, is provided on the etch stop layer in a gate region.
7 . The semiconductor structure of claim 1 , wherein a material of the etch stop layer is a material having a difference from the P-type semiconductor layer in an etch rate.
8 . The semiconductor structure of claim 1 , wherein a thickness of the etch stop layer ranges from 0.1 nm to 10 nm.
9 . The semiconductor structure of claim 1 , wherein a nucleation layer and a buffer layer are provided from bottom to top between the semiconductor substrate and the back barrier layer.
10 . The semiconductor structure of claim 4 , wherein the material of the etch stop layer comprises at least one of p-AlN, p-AlGaN, an alternating multilayer superlattice structure with p-GaN/p-AlGaN, or an alternating multilayer superlattice structure with p-AlGaN/p-AlN.
11 . A method of manufacturing a semiconductor substrate, comprising:
providing a semiconductor substrate;
forming a back barrier layer, a channel layer, an etch stop layer and a P-type semiconductor layer sequentially on the semiconductor substrate, wherein a two-dimensional hole gas is formed at an interface between the back barrier layer and the channel layer, the etch stop layer is vertically above the two-dimensional hole gas;
removing the P-type semiconductor layer in a gate region by etching, retaining the P-type semiconductor layer in a source region and the P-type semiconductor layer in a drain region; and
forming a P-type ion heavily doped layer respectively on the P-type semiconductor layer in the source region and the P-type semiconductor layer in the drain region.
12 . The method of claim 11 , wherein a material of the P-type semiconductor layer comprises a group III nitride material.
13 . The method of claim 11 , wherein a material of the etch stop layer-comprises at least one of: AlN, AlGaN, an alternating multilayer superlattice structure with GaN/AlGaN, or an alternating multilayer superlattice with AlGaN/AlN.
14 . The method of claim 11 , wherein a material of the etch stop layer-comprises at least one of p-AlN, p-AlGaN, an alternating multilayer superlattice structure with p-GaN/p-AlGaN, or an alternating multilayer superlattice structure with p-AlGaN/p-AlN.
15 . The method of claim 11 , wherein the channel layer comprises a group III nitride material.
16 . The method of claim 11 , further comprising: forming a source electrode on the P-type semiconductor layer in the source region;
forming a drain electrode on the P-type semiconductor layer in the drain region; and
forming a multi-layer structure, comprising a gate electrode insulating layer and a gate electrode, on the etch stop layer in the gate region.