Semiconductor structure and manufacturing method thereof
A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.
1 . A semiconductor structure, comprising:
a substrate; and
a heterojunction structure located on the substrate, wherein the heterojunction structure comprises a channel layer and a barrier layer located on the channel layer; and the channel layer comprises at least one n-type doped layer;
wherein a lowest layer of the at least one n-type doped layer is located at an interface of the channel layer close to the substrate.
2 . The semiconductor structure according to claim 1 , further comprising: a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is located on the barrier layer, and the source electrode and the drain electrode are located on two sides of the gate electrode separately.
3 . The semiconductor structure according to claim 1 , wherein the channel layer comprises a plurality of n-type doped layers, and the plurality of n-type doped layers are spaced in a direction of a thickness of the channel layer.
4 . The semiconductor structure according to claim 3 , wherein doping concentrations of the plurality of n-type doped layers vary in gradient.
5 . The semiconductor structure according to claim 4 , wherein in a direction where the substrate points towards the barrier layer, the doping concentrations of the plurality of n-type doped layers gradually decrease.
6 . The semiconductor structure according to claim 3 , wherein in a direction where the substrate points towards the barrier layer, thicknesses of the plurality of n-type doped layers vary in gradient.
7 . The semiconductor structure according to claim 1 , wherein at least one of the at least one n-type doped layer is a wide bandgap semiconductor layer comprising In element.
8 . The semiconductor structure according to claim 7 , wherein in a direction where the substrate points towards the barrier layer, a content of In element in the at least one of the at least one n-type doped layer gradually decreases.
9 . The semiconductor structure according to claim 3 , wherein the plurality of n-type doped layers are wide bandgap semiconductor layers comprising In elements; in a direction where the substrate points towards the barrier layer, contents of In element in the plurality of n-type doped layers gradually decrease.
10 . The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprises a back barrier layer located between the substrate and the heterojunction structure.
11 . The semiconductor structure according to claim 2 , further comprising:
a heavily doped n-type semiconductor layer, which is located at both sides of the heterojunction structure; wherein the heavily doped n-type semiconductor layer extends into the channel layer, and the source electrode and the drain electrode are located on the heavily doped n-type semiconductor layer.
12 . The semiconductor structure according to claim 11 , wherein in a direction where the channel layer points towards the barrier layer, a width of the heavily doped n-type semiconductor layer varies in a gradient decrease, a linear decrease, or a combination of a gradient decrease and a linear decrease.
13 . A method of manufacturing semiconductor substrate, comprising:
providing a substrate;
forming a heterojunction structure on the substrate, wherein forming the heterojunction structure on the substrate comprises: forming a channel layer on the substrate, doping the channel layer to form at least one n-type doped layer, and forming a barrier layer on the channel layer; and
forming a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the gate electrode separately;
wherein a lowest layer of the at least one n-type doped layer is located at an interface of the channel layer close to the substrate.
14 . The method according to claim 13 , wherein the channel layer comprises a plurality of n-type doped layers, and the plurality of n-type doped layers are spaced in a direction of a thickness of the channel layer.
15 . The method according to claim 14 , wherein at least one of: doping concentrations of the plurality of n-type doped layers vary in gradient, or thicknesses of the plurality of n-type doped layers vary in gradient.
16 . The method according to claim 13 , wherein at least one of the at least one n-type doped layer is a wide bandgap semiconductor layer comprising In element.
17 . The method according to claim 13 , wherein the heterojunction structure comprises a gate region, and the gate electrode is located on the gate region; after forming the heterojunction structure located on the substrate, the method further comprises:
etching parts of the channel layer and the barrier layer located at two sides of the gate region;
laterally etching the channel layer further;
growing a heavily doped n-type semiconductor layer on a side of the channel layer and a side of the barrier layer; wherein the heavily doped n-type semiconductor layer extends into the channel layer.
18 . The method according to claim 17 , wherein in a direction where the channel layer points towards the barrier layer, a width of the heavily doped n-type semiconductor layer varies in a gradient decrease, a linear decrease, or a combination of a gradient decrease and a linear decrease.