Inner spacer liner for gate-all-around device
Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.
1 . A method of manufacturing an electronic device, the method comprising:
forming a superlattice structure on a top surface of a semiconductor substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs;
recessing a portion of each semiconductor material layer of the plurality of semiconductor material layers to form a plurality of recessed semiconductor material layers;
forming an amorphous silicon liner conformally along the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers; and
forming a dielectric inner spacer directly on the amorphous silicon liner, wherein the dielectric inner spacer is adjacent a source region and a drain region, wherein
the amorphous silicon liner and the dielectric inner spacer are formed by a same deposition process in a single step.
2 . The method of claim 1 , further comprising precleaning the semiconductor substrate prior to the forming the amorphous silicon liner and the forming the dielectric inner spacer.
3 . The method of claim 2 , wherein the precleaning the semiconductor substrate, the forming the amorphous silicon liner, and the forming the inner spacer are performed in an integrated tool system without vacuum break.
4 . The method of claim 1 , wherein the amorphous silicon liner has a thickness in a range of from 0.5 nm to 3 nm.
5 . The method of claim 1 , the amorphous silicon liner and the dielectric inner spacer are formed by a chemical vapor deposition (CVD) process at a temperature in a range of from 400° C. to 650° C.
6 . The method of claim 1 , wherein the dielectric inner spacer comprises a low-K dielectric material.
7 . The method of claim 6 , wherein the low-κ dielectric material has a κ-value of in a range of from 3 to 5.
8 . The method of claim 6 , wherein the low-κ dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).
9 . The method of claim 1 , wherein each of the amorphous silicon liner and the dielectric inner spacer are substantially free of seams and/or voids.
10 . The method of claim 1 , wherein the plurality of semiconductor material layers comprises silicon germanium (SiGe) and the corresponding plurality of channel layers comprises silicon (Si).
11 . The method of claim 1 , further comprising etching a portion of the dielectric inner spacer.
12 . A method of manufacturing a gate-all-around (GAA) device, the method comprising:
precleaning a semiconductor substrate, the semiconductor substrate having a superlattice structure and a replacement metal gate formed on a top surface of the substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs;
performing a single step chemical vapor deposition (CVD) process to form an amorphous silicon liner and a dielectric inner spacer within the superlattice structure, the amorphous silicon liner conformally formed along the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers, the dielectric inner spacer formed directly on the amorphous silicon liner, the dielectric inner spacer adjacent a source region and a drain region;
etching an outer portion of the inner spacer; and
removing the replacement metal gate and the plurality of recessed semiconductor material layers from the semiconductor substrate, followed by etching an inner sidewall portion of the amorphous silicon liner.
13 . The method of claim 12 , further comprising forming an interlayer dielectric (ILD) on the plurality of channel layers after the etching the inner sidewall portion of the amorphous silicon liner.
14 . The method of claim 13 , wherein the precleaning the semiconductor substrate and the performing the single step chemical vapor deposition (CVD) process to form the amorphous silicon liner and the dielectric inner spacer within the superlattice structure are performed in an integrated tool system without vacuum break.
15 . The method of claim 13 , wherein the amorphous silicon liner and the dielectric inner spacer are formed at a temperature in a range of from 400° C. to 650° C.
16 . The method of claim 13 , wherein each of the amorphous silicon liner and the dielectric inner spacer are substantially free of seams and/or voids.
17 . The method of claim 13 , wherein the amorphous silicon liner has a thickness in a range of from 0.5 nm to 3 nm.
18 . The method of claim 13 , wherein the dielectric inner spacer comprises a low-K dielectric material having a K-value of in a range of from 3 to 5.
19 . The method of claim 18 , wherein the low-κ dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).
20 . The method of claim 12 , further comprising forming a high-k dielectric material on the ILD.