Semiconductor structure and method manufacturing the same

1 . A semiconductor structure, comprising:

a substrate;

a plurality of source/drain (S/D) regions disposed in the substrate;

a backside contact, disposed above the plurality of S/D regions;

a first dielectric layer disposed between the backside contact and the plurality of S/D regions; and

a conductive via, extended through the first dielectric layer to electrically connect the plurality of S/D regions and the backside contact, wherein the conductive via comprises an anisotropic transport material,

wherein the backside contact comprises materials having isotropic conductivity, and directional conductivities of the backside contact and the conductive via are different from each other.

2 . The semiconductor structure of claim 1 , further comprising a barrier layer disposed between the backside contact and the conductive via.

3 . The semiconductor structure of claim 1 , wherein a top surface of the conductive via is exposed from a barrier layer, and the backside contact is in direct contact with the conductive via.

4 . The semiconductor structure of claim 1 , further comprising a hard mask layer disposed between the backside contact and the first dielectric layer.

5 . The semiconductor structure of claim 1 , further comprising a capping layer disposed between the backside contact and the conductive via.

6 . The semiconductor structure of claim 1 , wherein the conductive via comprises a protrusion portion protruding toward the backside contact, and a barrier layer is disposed between the protrusion portion and the backside contact.

7 . The semiconductor structure of claim 1 , wherein the anisotropic transport material comprises M n+1 AX phases,

wherein M are early transition metals comprising Sc, Cr, Zr, Nb, Mo, or Hf, n is equal to 1 to 4, A are elements comprising Zn, Cd, Ga, In, Ti, Ge, Sn, Pb, P, As, or S, and X are elements comprising C.

8 . A semiconductor structure, comprising:

a substrate;

a first dielectric layer, disposed over the substrate;

a plurality of source/drain (S/D) regions, disposed in the substrate;

a first contact, penetrating through the first dielectric layer to electrically connect the plurality of S/D regions;

a second dielectric layer, disposed below the plurality of S/D regions;

a second contact, penetrating through the second dielectric layer; and

a conductive via, penetrating through the substrate to electrically connect the first contact and the second contact, wherein the plurality of S/D regions is disposed aside the conductive via, and the conductive via comprises an anisotropic transport material,

wherein the first contact and the second contact comprise materials different from materials of the conductive via,

wherein directional conductivities of the first contact and the second contact are different from directional conductivity of the conductive via.

9 . The semiconductor structure of claim 8 , further comprising a cutting metal gate laterally disposed aside the plurality of S/D regions and the conductive via.

10 . The semiconductor structure of claim 8 , further comprising a capping layer disposed between the first contact and the conductive via.

11 . The semiconductor structure of claim 8 , further comprising a barrier liner disposed between the first contact and the conductive via.

12 . The semiconductor structure of claim 8 ,

wherein the material of the first contact comprises a topological material.

13 . The semiconductor structure of claim 8 ,

wherein the material of the second contact comprises a topological material.

14 . A method of manufacturing a semiconductor structure, comprising:

providing a substrate having a plurality of source/drain (S/D) regions formed therein;

forming a first dielectric layer over the substrate;

forming a second dielectric layer below the first dielectric layer and the plurality of S/D regions;

forming a first contact penetrating through the first dielectric layer;

forming a second contact penetrating through the second dielectric layer; and

forming a conductive via penetrating through the substrate to electrically connect the first contact and the second contact,

wherein the conductive via is formed of an anisotropic transport material,

wherein the first contact and the second contact comprise forming materials different from the forming material of the conductive via,

wherein directional conductivities of the first contact and the second contact are different from directional conductivity of the conductive via.

15 . The method of claim 14 , further comprising forming a third dielectric layer and a third contact below the plurality of S/D regions and aside the conductive via.

16 . The method of claim 14 , further comprising forming an oxide-filled trench embedded the substrate prior to the step of forming the conductive via.

17 . The method of claim 14 , further comprising forming a cutting metal gate laterally disposed aside the plurality of S/D regions and the conductive via.

18 . The method of claim 14 , further comprising forming a capping layer between the first contact and the conductive via.

19 . The method of claim 14 , further comprising forming a barrier liner disposed between the first contact and the conductive via.

20 . The method of claim 14 , further comprising forming a hard mask layer on the second dielectric layer.