IP Library Granted Patent US 12690227
Granted Patent B2
US 12690227 · App. 18/384,121 · Granted Jul 21, 2026

Semiconductor device

Inventors: Masahiro Sugimoto (Kyoto, JP); Shinpei Matsuda (Kyoto, JP); Yasushi Higuchi (Kyoto, JP); Kazuyoshi Norimatsu (Kyoto, JP)
Assignee: FLOSFIA INC.
H10D30/66H10D62/80H10D99/00H10P14/24H10P14/3434H02P27/06
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690227
App. No.
18/384,121
Granted
Jul 21, 2026
Kind
B2
Abstract

Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region. The current blocking region is composed of a high-resistance layer. The source electrode forms a contact with the current blocking region.

Claims (18)

1 . A semiconductor device comprising at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region,

the current blocking region being composed of a high-resistance layer, the source electrode being in direct contact with the current blocking region.

2 . The semiconductor device according to claim 1 , wherein

the crystalline oxide semiconductor layer contains at least one type of metal selected from aluminum, indium, and gallium.

3 . The semiconductor device according to claim 1 , wherein

the crystalline oxide semiconductor layer has a corundum structure.

4 . The semiconductor device according to claim 1 , wherein

the current blocking region contains a dopant.

5 . The semiconductor device according to claim 4 , wherein

the dopant in the current blocking region has a concentration equal to or greater than 1.0××10 17 /cm 3 .

6 . The semiconductor device according to claim 1 , wherein

the current blocking region is an ion-implanted region.

7 . The semiconductor device according to claim 1 , wherein

electron trap density in the current blocking region is equal to or greater than 4.0×10 18 /cm 3 .

8 . The semiconductor device according to claim 1 , wherein

the semiconductor device is a transistor.

9 . A power converter that uses the semiconductor device according to claim 1 .

10 . A control system that uses the semiconductor device according to claim 1 .