Semiconductor device with split-gate and method forming the same

1 . A semiconductor device, comprising:

a substrate having a first conductive type;

an epitaxial layer disposed on the substrate, wherein the epitaxial layer has the first conductive type;

a doped region disposed in the epitaxial layer, wherein the doped region has a second conductive type different from the first conductive type;

a gate electrode disposed through the doped region and extending into the epitaxial layer, wherein the gate electrode comprising:

a first structure having a first dimension; and

a second structure above the first structure, wherein the second structure comprises a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension, wherein a bottom surface of the protruding portion is lower than a bottommost surface of the main portion, wherein a lateral dimension of the main portion is larger than a maximum lateral dimension of the protruding portion, and a sidewall of the main portion and a sidewall of the protruding portion are discontinuous, wherein a portion of a bottom surface of the main portion close to the protruding portion is planar; and

a gate dielectric layer disposed on the gate electrode, wherein a top of the gate dielectric layer and a top surface of the gate electrode are levelled, wherein the gate dielectric layer comprises a first portion disposed on opposite sides and a bottom of the first structure, and a second portion disposed on opposite sides of the second structure, wherein the first portion is entirely separated from the second portion in a vertical projection, wherein the first portion is disposed in a first opening of a gate trench, and the second portion is disposed in a second opening of the gate trench, wherein the first opening has a first width, and the second opening has a second width larger than the first width.

2 . The semiconductor device of claim 1 , wherein the gate dielectric layer further comprising:

a third portion disposed between the first structure and the protruding portion of the second structure.

3 . The semiconductor device of claim 1 , wherein the protruding portion of the second structure is vertically located between the first structure and the main portion of the second structure.

4 . The semiconductor device of claim 1 , further comprising a well region disposed in the doped region, wherein the well region has the first conductive type.

5 . The semiconductor device of claim 4 , wherein the main portion of the second structure of the gate electrode is disposed through the well region and extends into the doped region.

6 . The semiconductor device of claim 1 , wherein the protruding portion of the second structure of the gate electrode is entirely disposed in the doped region.

7 . The semiconductor device of claim 1 , wherein the first structure of the gate electrode is disposed across the doped region and the epitaxial layer.

8 . The semiconductor device of claim 4 , further comprising an interlayer dielectric (ILD) layer disposed on the epitaxial layer and the gate electrode.

9 . The semiconductor device of claim 8 , further comprising a source electrode disposed through the interlayer dielectric layer and extending into the well region.

10 . The semiconductor device of claim 9 , further comprising a doped contact region below the source electrode and extending into the doped region, wherein the doped contact region has the second conductive type.

11 . The semiconductor device of claim 1 , further comprising a drain electrode disposed on another side of the substrate opposite the epitaxial layer.