Semiconductor device comprising mutually separated trench structures

1 . A semiconductor device comprising a plurality of mutually separated trench structures, each trench structure comprising:

an elongated trench formed in a semiconductor body;

wherein the elongated trench extends through an active area in the semiconductor body;

a first dielectric layer arranged on a bottom and a lower portion of a sidewall of the elongated trench;

a first polysilicon body arranged in the elongated trench and separated from the bottom and a sidewall of the elongated trench by the first dielectric layer;

a second dielectric layer arranged, within the active area, on an upper portion of the sidewall of the elongated trench, on the first polysilicon body, and on the first dielectric layer;

a second polysilicon body arranged, within the active area, in the elongated trench and separated from the sidewall of the elongated trench and from the first polysilicon body by the second dielectric layer;

wherein the second polysilicon body comprises an elongated recess extending along the elongated trench within the active area, the elongated recess being directed to the bottom of the elongated trench;

wherein the first polysilicon body has a tapered upper end that extends along the elongated trench within the active area and that partially extends in the elongated recess;

wherein a minimum thickness d1 of the second dielectric layer between the tapered upper end and the second polysilicon body is greater than a minimum thickness d2 of the second dielectric layer between the upper portion of the sidewall and the second polysilicon body;

wherein the semiconductor body comprises an access area and an intermediate area through which the elongated trench extends;

wherein the intermediate area is arranged in between the access area and the active area;

wherein, in the access area, the first polysilicon body fills the elongated trench and the second polysilicon body is absent, and

wherein d1 is greater in the intermediate area than inside the active area.

2 . The semiconductor device according to claim 1 , wherein d1=a×d2, wherein a>2 and wherein d2 lies in a range between 0.02 and 0.2 micrometer.

3 . The semiconductor device according to claim 1 , wherein the first polysilicon body has a maximum width w1 in a direction perpendicular to a longitudinal axis of the elongated trench, wherein the tapered upper end has a height h1 in a depth direction of the elongated trench, wherein 0.3<w1/h1<3, and wherein width w1 lies in a range between 0.1 and 2 micrometers.

4 . The semiconductor device according to claim 1 , wherein the first dielectric layer and the second dielectric layer are both silicon oxide layers.

5 . The semiconductor device according to claim 1 , wherein the semiconductor device is a shielded gate field-effect transistor;

wherein the first polysilicon body forms a shielded gate for the transistor;

wherein the second polysilicon body forms a gate for the transistor; and

wherein a part of the second dielectric layer in between the second polysilicon body and the upper portion of the sidewall of the elongated trench forms a gate oxide for the transistor.

6 . The semiconductor device according to claim 1 , wherein the semiconductor body comprises a silicon body.

7 . The semiconductor device according to claim 1 , wherein d2 lies in a range between 0.03 and 0.07 micrometer.

8 . The semiconductor device according to claim 1 , wherein d1=a×d2, wherein a>3 and wherein d2 lies in a range between 0.02 and 0.2 micrometer.

9 . A method for manufacturing a semiconductor device comprising a plurality of mutually separated trench structures, the method comprising the steps of:

a) providing a plurality of spaced apart elongated trenches formed in a semiconductor body, each elongated trench extending through an active area in the semiconductor body;

wherein each elongated trench has a bottom and a lower portion of a sidewall covered by a first dielectric layer; and

wherein for each elongated trench is a first polysilicon body that is arranged in the elongated trench;

wherein the first polysilicon body is separated from the bottom and the sidewall of the elongated trench by the first dielectric layer;

wherein for each elongated trench, an upper surface of the first polysilicon body and an upper portion of the sidewall are exposed;

b) performing a wet thermal oxidation for oxidizing the first polysilicon body and the exposed upper surface of the sidewall for forming, within the active area, a first part of a second dielectric layer and subsequently performing a dry thermal oxidation for forming a remaining part of the second dielectric layer;

c) arranging within the active area a second polysilicon body on the second dielectric layer in each elongated trench so that the second polysilicon body is separated from the sidewall of the elongated trench and from the first polysilicon body by the second dielectric layer;

wherein the semiconductor body comprises an access area and an intermediate area through which the plurality of elongated trenches extend,

wherein the intermediate area is arranged in between the access area and the active area; and

wherein the method further comprises

forming the second dielectric layer so that a minimum thickness d1 of the second dielectric layer between a tapered upper end of the first polysilicon body and the second polysilicon body is greater than a minimum thickness d2 of the second dielectric layer between an upper portion of the sidewall of the elongated trench and the second polysilicon body;

wherein, in the access area, the elongated trench is formed so that the first polysilicon body fills the elongated trench and the second polysilicon body is absent, and

wherein d1 is greater in the intermediate area than inside the active area.

10 . The method according to claim 9 , wherein during the wet oxidation of the first polysilicon body, an oxidation rate is at least 3 times greater than that of the exposed upper portion of the sidewall of the elongated trench.

11 . The method according to claim 9 , wherein performing step a) further comprises performing the steps of:

a1) providing the plurality of spaced apart elongated trenches so that the bottom and the sidewall of each elongated trench are covered by the first dielectric layer;

wherein for each elongated trench the first polysilicon body is arranged in the elongated trench, and the first polysilicon body is separated from the bottom and sidewall of the elongated trench by the first dielectric layer; and

wherein for each elongated trench an upper surface of the first polysilicon body is exposed;

a2) performing thermal oxidation and subsequent deposition to round off the upper surface of the first polysilicon body thereby forming the tapered upper end of the first polysilicon body and thickening the first dielectric layer;

a3) arranging a first masking layer;

a4) opening the first masking layer within the active area;

a5) etching the first dielectric layer through the opened first masking layer so that the upper portion of the sidewall of each elongated trench becomes exposed and so that the tapered upper end of the first polysilicon body protrudes from the first dielectric layer.

12 . The method according to claim 10 , wherein performing step a) further comprises performing the steps of:

a1) providing the plurality of spaced apart elongated trenches so that the bottom and the sidewall of each elongated trench are covered by the first dielectric layer;

wherein for each elongated trench the first polysilicon body is arranged in the elongated trench, and the first polysilicon body is separated from the bottom and sidewall of the elongated trench by the first dielectric layer; and

wherein for each elongated trench, an upper surface of the first polysilicon body is exposed;

a2) performing thermal oxidation and subsequent deposition to round off the upper surface of the first polysilicon body thereby forming the tapered upper end of the first polysilicon body and thickening the first dielectric layer;

a3) arranging a first masking layer;

a4) opening the first masking layer within the active area;

a5) etching the first dielectric layer through the opened first masking layer so that the upper portion of the sidewall of each elongated trench becomes exposed and so that the tapered upper end of the first polysilicon body protrudes from the first dielectric layer.

13 . The method according to claim 11 , wherein the etching under step a5) is performed so that after having completed steps b) and c) a recess is formed in the second polysilicon body in which the upper and of the first polysilicon body protrudes.

14 . The method according to claim 11 , wherein the step a1) further comprises:

a11) providing the plurality of spaced apart elongated trenches so that the bottom and the sidewall of each elongated trench and an upper surface of the semiconductor body are covered by the first dielectric layer; and

a12) etching the first dielectric layer to expose the upper surface of the semiconductor body.

15 . The method according to claim 13 , wherein the step a1) further comprises:

a11) providing the plurality of spaced apart elongated trenches so that the bottom and the sidewall of each elongated trench and an upper surface of the semiconductor body are covered by the first dielectric layer; and

a12) etching the first dielectric layer to expose the upper surface of the semiconductor body.

16 . The method according to claim 14 , wherein the semiconductor body comprises an access area and an intermediate area through which the plurality of elongated trenches extend;

wherein the intermediate area is arranged in between the access area and the active area, and wherein the step a11) further comprises:

a111) providing the plurality of spaced apart elongated trenches so that the bottom and the sidewall of each elongated trench and an upper surface of the semiconductor body are covered by the first dielectric layer and wherein the first polysilicon body fills the elongated trench;

a112) providing a second masking layer;

a113) patterning the second masking layer so that the second masking layer covers those elongated trenches among the plurality of elongated trenches that are arranged in an access area, and so that the second masking layer exposes those elongated trenches among the plurality of elongated trenches that are arranged in the active area;

a114) partially etching the first polysilicon body in the plurality of elongated trenches through the opened second masking layer;

a115) partially etching, the first dielectric layer so that the tapered upper end of the first polysilicon body protrudes from the first dielectric layer;

a116) etching the first polysilicon body.

17 . The method according to claim 16 , wherein step a114) is performed so that after the etching, the first polysilicon body inside the intermediate area varies from a level corresponding to that of the first polysilicon body inside the active area to a level corresponding to that of the first polysilicon body inside the access area.

18 . The method according to claim 16 , wherein step a116) is performed so that after the etching, the first polysilicon body within the active area lies leveled with the first dielectric layer, and so that after the etching, the first polysilicon body within the access area lies in plane with the upper surface of the semiconductor body.

19 . The method according to claim 17 , wherein step a116) is performed so that after the etching, the first polysilicon body within the active area lies leveled with the first dielectric layer, and so that after the etching, the first polysilicon body within the access area lies in plane with the upper surface of the semiconductor body.