Raised source/drain oxide semiconducting thin film transistor and methods of making the same
A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.
1 . A transistor, comprising:
a patterned gate electrode;
a dielectric layer located over the patterned gate electrode;
a patterned first oxide semiconductor layer comprising a first oxide semiconductor material composition and including a central portion including a channel region and outer portions on opposing sides of the central portion comprising a lower portion of source/drain regions;
a patterned second oxide semiconductor layer comprising an upper portion of the source/drain regions located on the outer portions of the patterned first oxide semiconductor layer, wherein a thickness of the source/drain regions is greater than a thickness of the channel region, the patterned second oxide semiconductor layer comprises a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the patterned second oxide semiconductor layer contacts the patterned first oxide semiconductor layer;
an interconnect level dielectric material layer contacting an upper surface of the central portion of the patterned first oxide semiconductor layer at a contact location, wherein the patterned second oxide semiconductor layer is on opposing sides of the interconnect level dielectric material layer at the contact location; and
a pair of metal contacts comprising:
a bottom surface contacting an upper surface of the patterned second oxide semiconductor layer across an entire width of the patterned second oxide semiconductor layer; and
an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the patterned second oxide semiconductor layer and with a sidewall of the patterned first oxide semiconductor layer, wherein a thickness of the source/drain regions comprises a combined thickness of the patterned second oxide semiconductor layer and the patterned first oxide semiconductor layer, and a ratio of the thickness of the source/drain regions to a thickness of the channel region of the patterned first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the patterned gate electrode is under the pair of metal contacts and a bottom surface of the dielectric layer contacts the interconnect level dielectric material layer under the pair of metal contacts.
2 . The transistor of claim 1 , wherein the dielectric layer comprises one of SiO 2 , Al 2 O 3 , HfO 2 , HZO, HfSiO x , HfLaO x , or a multilayer thereof.
3 . The transistor of claim 1 , wherein the first oxide semiconductor material composition comprises one of In x Ga y ZnzO w , In 2 O 3 , Ga 2 O 3 , ZnO, or In x Sn y O z .
4 . The transistor of claim 1 , wherein an upper surface of the pair of metal contacts is coplanar with an upper surface of the interconnect level dielectric material layer.
5 . The transistor of claim 1 , wherein the interconnect level dielectric material layer comprises a trench and the patterned gate electrode is located in the trench.
6 . The transistor of claim 5 , wherein the dielectric layer comprises an outer portion located on the interconnect level dielectric material layer outside the trench.
7 . The transistor of claim 1 , wherein the second oxide semiconductor material composition comprises In x Ga y Zn z O w .
8 . The transistor of claim 1 , wherein a thickness of the dielectric layer is in a range from 2 nm to 8 nm, a thickness of the patterned gate electrode is in a range from 2 nm to 16 nm, a thickness of the patterned first oxide semiconductor layer in the channel region is in a range from 2 nm to 8 nm, and the combined thickness of the patterned second oxide semiconductor layer and the patterned first oxide semiconductor layer is in a range from 8 nm to 16 nm.
9 . The transistor of claim 1 , wherein the pair of metal contacts comprises a first metal contact and a second metal contact, and a length of the patterned gate electrode is greater than a distance between a center of the first metal contact and a center of the second metal contact and less than a distance between the outer sidewall of the first metal contact and the outer sidewall of the second metal contact.
10 . The transistor of claim 9 , wherein a length of the bottom surface of the dielectric layer contacting the interconnect level dielectric material layer is greater than a thickness of the dielectric layer.
11 . The transistor of claim 10 , wherein the interconnect level dielectric material layer comprises at least one of undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, the pair of metal contacts further comprises an inner sidewall, and an entirety of the inner sidewall contacts the interconnect level dielectric material layer.
12 . A transistor, comprising:
a gate electrode;
a gate dielectric layer on the gate electrode;
a channel region on the gate dielectric layer, comprising a central portion of a first oxide semiconductor layer, wherein the first oxide semiconductor layer comprises a first oxide semiconductor material composition;
source/drain regions on the gate dielectric layer, comprising a pair of outer portions of the first oxide semiconductor layer on opposing sides of the central portion, and a second oxide semiconductor layer on the pair of outer portions of the first oxide semiconductor layer, wherein a thickness of the source/drain regions is greater than a thickness of the channel region, the second oxide semiconductor layer comprises a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the second oxide semiconductor layer contacts the first oxide semiconductor layer;
an interconnect level dielectric material layer contacting an upper surface of the central portion of the first oxide semiconductor layer at a contact location, wherein the second oxide semiconductor layer is on opposing sides of the interconnect level dielectric material layer at the contact location; and
a pair of metal contacts comprising:
a bottom surface contacting an upper surface of the second oxide semiconductor layer across an entire width of the second oxide semiconductor layer; and
an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the second oxide semiconductor layer and with a sidewall of the first oxide semiconductor layer, wherein a thickness of the source/drain regions comprises a combined thickness of the second oxide semiconductor layer and the first oxide semiconductor layer, and a ratio of the thickness of the source/drain regions to a thickness of the channel region of the first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the gate electrode is under the pair of metal contacts and a bottom surface of the gate dielectric layer contacts the interconnect level dielectric material layer under the pair of metal contacts.
13 . The transistor of claim 12 , wherein each of the first oxide semiconductor material composition and the second oxide semiconductor material composition comprises one of In x Ga y Zn z O w , In 2 O 3 , Ga 2 O 3 , ZnO, or In x Sn y O z .
14 . The transistor of claim 12 , wherein a bottom surface of the second oxide semiconductor layer contacts an upper surface of the first oxide semiconductor layer.
15 . The transistor of claim 12 , wherein a length of the channel region is in a range from 15 nm to 150 nm, a length of the source/drain regions is in a range from 15 nm to 150 nm, and a length of the gate electrode is greater than the length of the channel region, such that the source/drain regions are located over the gate electrode.
16 . The transistor of claim 12 , wherein the source/drain regions comprise:
a first source/drain region including a first portion of the second oxide semiconductor layer; and
a second source/drain region including a second portion of the second oxide semiconductor layer that is separate from the first portion of the second oxide semiconductor layer.
17 . A semiconductor device, comprising:
a metal layer;
a dielectric layer on the metal layer;
a first oxide semiconductor layer on the dielectric layer comprising a first oxide semiconductor material composition and including a central portion and a pair of outer portions on opposing sides of the central portion;
an interconnect level dielectric (ILD) layer contacting the central portion of the first oxide semiconductor layer at a contact location;
a pair of second oxide semiconductor layer portions in the ILD layer on the pair of outer portions of the first oxide semiconductor layer, respectively, wherein the pair of second oxide semiconductor layer portions are on opposing sides of the ILD layer at the contact location, the pair of second oxide semiconductor layer portions comprise a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the pair of second oxide semiconductor layer portions contact the first oxide semiconductor layer; and
a pair of metal contacts comprising:
a bottom surface contacting an upper surface of the pair of second oxide semiconductor layer portions across an entire width of the pair of second oxide semiconductor layer portions; and
an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the pair of second oxide semiconductor layer portions and with a sidewall of the first oxide semiconductor layer, wherein a ratio of a combined thickness of the pair of second oxide semiconductor layer portions and the first oxide semiconductor layer to a thickness of the first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the metal layer is under the pair of metal contacts and a bottom surface of the dielectric layer contacts the ILD layer under the pair of metal contacts.
18 . The semiconductor device of claim 17 , wherein the metal layer, the dielectric layer, the first oxide semiconductor layer and the second oxide semiconductor layer are embedded in the ILD layer.
19 . The semiconductor device of claim 17 , wherein an upper surface of the pair of metal contacts is coplanar with an upper surface of the ILD layer.
20 . The semiconductor device of claim 17 , wherein the semiconductor device comprises a transistor comprising:
a channel region comprising the central portion of the first oxide semiconductor layer; and
an active region contacting the channel region and comprising the pair of outer portions of the first oxide semiconductor layer and the second oxide semiconductor layer.
21 . The semiconductor device of claim 20 , wherein a thickness of the active region is greater than a thickness of the channel region.
22 . The semiconductor device of claim 20 , wherein a conductivity of the active region is greater than a conductivity of the channel region.