IP Library › Granted Patent US 12690235
Granted Patent B2
US 12690235 · App. 17/544,724 · Granted Jul 21, 2026

Gate-all-around integrated circuit structures having depopulated channel structures using directed bottom-up approach

Inventors: Leonard P. Guler (Hillsboro, OR); Clifford Ong (Portland, OR); Mohammad Hasan (Aloha, OR); Tahir Ghani (Portland, OR); Charles H. Wallace (Portland, OR)
Assignee: Intel Corporation
H10D30/6735H10D30/014H10D30/0198H10D30/43H10D30/6757H10D62/121H10D64/01H10D64/258H10D84/0128H10D84/013H10D84/83
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Quick Facts
Patent No.
US 12690235
App. No.
17/544,724
Granted
Jul 21, 2026
Kind
B2
Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a directed bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. A gate stack is over and around the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein at least one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires.

Claims (48)

1 . An integrated circuit structure, comprising:

a first vertical arrangement of nanowires;

a gate stack over and around the first vertical arrangement of nanowires, wherein a bottommost surface of the gate stack is below a bottommost nanowire of the first vertical arrangement of nanowires;

a first epitaxial source or drain structure at a first end of the first vertical arrangement of nanowires;

a second epitaxial source or drain structure at a second end of the first vertical arrangement of nanowires, the second end opposite the first end, wherein one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the first vertical arrangement of nanowires;

a second vertical arrangement of nanowires laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires in contact with the one of the first or second epitaxial source or drain structures; and

a liner dielectric layer having a first internal spacer portion between nanowires of the first vertical arrangement of nanowires, a second internal spacer portion between nanowires of the second vertical arrangement of nanowires, and a cavity liner portion beneath the one of the first or second epitaxial source or drain structures, the cavity liner portion continuous with the first internal spacer portion and with the second internal spacer portion.

2 . The integrated circuit of claim 1 , wherein the one of the first or second epitaxial source or drain structures is not coupled to one or more bottommost ones of the first vertical arrangement of nanowires.

3 . The integrated circuit of claim 1 , wherein the one of the first or second epitaxial source or drain structures is on a dielectric structure that does not extend beneath the first vertical arrangement of nanowires.

4 . The integrated circuit of claim 1 , further comprising:

a first conductive contact structure coupled to the first epitaxial source or drain structure; and

a second conductive contact structure coupled to the second epitaxial source or drain structure.

5 . The integrated circuit structure of claim 4 , wherein the first and second conductive contact structures are an asymmetric pair of conductive contact structures.

6 . The integrated circuit of claim 1 , wherein the first vertical arrangement of nanowires comprises silicon, and wherein the first and second epitaxial source or drain structures comprise silicon and germanium.

7 . The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

8 . A method of fabricating an integrated circuit structure, the method comprising:

forming a first vertical arrangement of nanowires;

forming a gate stack over and around the first vertical arrangement of nanowires, wherein a bottommost surface of the gate stack is below a bottommost nanowire of the first vertical arrangement of nanowires;

forming a first epitaxial source or drain structure at a first end of the first vertical arrangement of nanowires;

forming a second epitaxial source or drain structure at a second end of the first vertical arrangement of nanowires, the second end opposite the first end, wherein one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires;

forming a second vertical arrangement of nanowires laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires in contact with the one of the first or second epitaxial source or drain structures; and

forming a liner dielectric layer having a first internal spacer portion between nanowires of the first vertical arrangement of nanowires, a second internal spacer portion between nanowires of the second vertical arrangement of nanowires, and a cavity liner portion beneath the one of the first or second epitaxial source or drain structures, the cavity liner portion continuous with the first internal spacer portion and with the second internal spacer portion.

9 . The method of claim 8 , wherein the one of the first or second epitaxial source or drain structures is not coupled to one or more bottommost ones of the first vertical arrangement of nanowires.

10 . The method of claim 8 , wherein the one of the first or second epitaxial source or drain structures is formed on a dielectric structure that does not extend beneath the first vertical arrangement of nanowires.

11 . The method of claim 8 , further comprising:

forming a first conductive contact structure coupled to the first epitaxial source or drain structure; and

forming a second conductive contact structure coupled to the second epitaxial source or drain structure.

12 . The method of claim 11 , wherein the first and second conductive contact structures are an asymmetric pair of conductive contact structures.

13 . The method of claim 8 , wherein the first vertical arrangement of nanowires comprises silicon, and wherein the first and second epitaxial source or drain structures comprise silicon and germanium.

14 . The method of claim 8 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

15 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a first vertical arrangement of nanowires;

a gate stack over and around the first vertical arrangement of nanowires, wherein a bottommost surface of the gate stack is below a bottommost nanowire of the first vertical arrangement of nanowires;

a first epitaxial source or drain structure at a first end of the first vertical arrangement of nanowires;

a second epitaxial source or drain structure at a second end of the first vertical arrangement of nanowires, the second end opposite the first end, wherein one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the first vertical arrangement of nanowires;

a second vertical arrangement of nanowires laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires in contact with the one of the first or second epitaxial source or drain structures; and

a liner dielectric layer having a first internal spacer portion between nanowires of the first vertical arrangement of nanowires, a second internal spacer portion between nanowires of the second vertical arrangement of nanowires, and a cavity liner portion beneath the one of the first or second epitaxial source or drain structures, the cavity liner portion continuous with the first internal spacer portion and with the second internal spacer portion.

16 . The computing device of claim 15 , further comprising:

a memory coupled to the board.

17 . The computing device of claim 15 , further comprising:

a communication chip coupled to the board.

18 . The computing device of claim 15 , further comprising:

a camera coupled to the board.

19 . The computing device of claim 15 , further comprising:

a battery coupled to the board.

20 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.