Memory transistor with multiple charge storage layers
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
1 . A memory device, comprising:
a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, wherein the channel is oriented substantially perpendicular to a semiconductor material structure;
a tunnel oxide layer surrounding the channel,
a multi-layer charge trapping layer surrounding the tunnel oxide layer,
a blocking oxide layer surrounding the multi-layer charge trapping layer;
a gate electrode surrounding the blocking oxide layer;
wherein the multi-layer charge trapping layer comprises a first nitride layer, a second nitride layer, and an oxide layer disposed between the first and second nitride layers; and
wherein each of the first and second nitride layers have a silicon component, an oxygen component and a nitrogen component.
2 . The memory device of claim 1 , wherein the tunnel oxide layer electrically isolates the multi-layer charge trapping layer from the channel.
3 . The memory device of claim 2 , wherein the tunnel oxide layer has a thickness that allows a charge to tunnel through the tunnel oxide layer and be trapped in the multi-layer charge trapping layer.
4 . The memory device of claim 1 , wherein the multi-layer charge trapping layer traps charge passing through the tunnel oxide layer.
5 . The memory device of claim 1 , wherein the oxide layer disposed between the first and second nitride layers is an anti-tunneling layer.
6 . The memory device of claim 5 , wherein the anti-tunneling layer substantially reduces a probability of an electron from tunneling into the first nitride layer from the second nitride layer, or vice-versa.
7 . The memory device of claim 1 , wherein the second nitride layer is oxygen-lean relative to the first nitride layer.
8 . The memory device of claim 7 , wherein the first nitride layer is located closer to the tunnel oxide layer than the blocking oxide layer.
9 . The memory device of claim 1 , wherein the first nitride layer is oxygen-rich relative to the second nitride layer.
10 . The memory device of claim 9 , wherein the first nitride layer is located closer to the tunnel oxide layer than the blocking oxide layer.
11 . The memory device of claim 1 , wherein the gate electrode is a high work function gate electrode.
12 . The memory device of claim 1 , wherein the blocking oxide layer includes a high K dielectric.
13 . The memory device of claim 1 , wherein the first and second nitride layers are silicon-rich.
14 . A memory device, comprising:
a gate structure;
a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, wherein the channel is vertical and oriented substantially perpendicular to a semiconductor material structure; and
a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel,
wherein the multi-layer charge trapping layer comprises a first dielectric layer, a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers, wherein the anti-tunneling layer includes an oxide layer, and wherein the first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride and wherein the blocking dielectric layer comprises a high K high dielectric.
15 . The memory device of claim 14 , wherein the tunnel dielectric layer surrounds the channel, the multi-layer charge trapping layer surround the tunnel dielectric layer, the blocking dielectric layer surrounds the multi-layer charge trapping layer; and the gate structure surrounds the blocking dielectric layer.
16 . The memory device of claim 14 , wherein the first and second dielectric layers each include a silicon component, an oxygen component and a nitrogen component.
17 . The memory device of claim 14 , wherein the tunnel dielectric layer electrically isolates the multi-layer charge trapping layer from the channel.
18 . The memory device of claim 17 , wherein the tunnel dielectric layer has a thickness that allows a charge to tunnel through the tunnel dielectric layer and be trapped in the multi-layer charge trapping layer.
19 . The memory device of claim 14 , wherein the multi-layer charge trapping layer traps charge passing through the tunnel dielectric layer.
20 . The memory device of claim 14 , wherein the anti-tunneling layer substantially reduces a probability of an electron from tunneling into the first dielectric layer from the second dielectric layer, or vice-versa.
21 . The memory device of claim 14 , wherein the second dielectric layer is oxygen-lean relative to the first dielectric layer.
22 . The memory device of claim 21 , wherein the first dielectric layer is located closer to the tunnel dielectric layer than the blocking dielectric layer.
23 . The memory device of claim 14 , wherein the first dielectric layer is oxygen-rich relative to the second dielectric layer.
24 . The memory device of claim 23 , wherein the first dielectric layer is located closer to the tunnel dielectric layer than the blocking dielectric layer.
25 . The memory device of claim 14 , wherein the gate structure includes a high work function gate electrode.