Semiconductor device
A semiconductor device includes a channel region formed on a substrate, a source region formed on the channel region, a drain region formed on the channel region, a gate region formed on the channel region between the source region and the drain region, a source contact region formed on a portion of the source region, and a resistance region formed on another portion of the source region. The source contact region and the resistance region are electrically connected in parallel with a source terminal.
1 . A semiconductor device comprising:
a channel region formed on a substrate;
a source region formed on the channel region;
a drain region formed on the channel region;
a gate region formed on the channel region between the source region and the drain region; and
a source contact region formed on a portion of the source region,
wherein the source region and the source contact region are electrically connected in parallel with a source terminal and
wherein the source contact region has an impurity concentration higher than that of the source region.
2 . A semiconductor device comprising:
a channel region formed on a substrate;
a source region formed on the channel region;
a drain region formed on the channel region;
a gate region formed on the channel region between the source region and the drain region;
a source contact region formed on a portion of the source region; and
a resistance region formed on another portion of the source region,
wherein the source contact region and the resistance region are electrically connected in parallel with a source terminal,
wherein the source contact region and the resistance region have a same conductivity type as the source region,
the source contact region has an impurity concentration higher than that of the source region, and
the resistance region has an impurity concentration equal to or lower than that of the source region.
3 . A semiconductor device comprising:
a channel region formed on a substrate;
a source region formed on the channel region;
a drain region formed on the channel region;
a gate region formed on the channel region between the source region and the drain region;
a source contact region formed on a portion of the source region; and
a resistance region formed on another portion of the source region,
wherein the source contact region and the resistance region are electrically connected in parallel with a source terminal,
wherein the source contact region has a same conductivity type as the source region, and
the resistance region has a conductivity type different from that of the source region.
4 . The semiconductor device of claim 3 , further comprising a gate contact region formed on the gate region,
wherein the gate region and the gate contact region have a same conductivity type as the resistance region, and
the resistance region has a same impurity concentration as the gate contact region.
5 . A semiconductor device comprising:
a channel region formed on a substrate;
a drain region formed on the channel region;
a gate region formed on the channel region to surround the drain region;
a source region formed on the channel region to surround the gate region;
at least one source contact region formed on the source region;
at least one resistance region formed on the source region; and
a device isolation region formed to surround the source region,
wherein the at least one source contact region and the at least one resistance region are electrically connected in parallel with a source terminal.
6 . The semiconductor device of claim 5 , wherein the substrate has a first conductivity type,
the channel region and the source region have a second conductivity type,
the at least one source contact region has the second conductivity type and has an impurity concentration higher than that of the source region, and
the at least one resistance region has the second conductivity type and has an impurity concentration equal to or lower than that of the source region.
7 . The semiconductor device of claim 5 , wherein the substrate has a first conductivity type,
the channel region and the source region have a second conductivity type,
the at least one source contact region has the second conductivity type, and
the at least one resistance region has the first conductivity type.
8 . The semiconductor device of claim 7 , further comprising a gate contact region formed on the gate region,
wherein the gate region and the gate contact region have the first conductivity type, and
the at least one resistance region has a same impurity concentration as the gate contact region.
9 . The semiconductor device of claim 5 , wherein a plurality of source contact regions is formed on the source region at regular intervals, and
a plurality of resistance regions is formed on the source region among the plurality of source contact regions.
10 . The semiconductor device of claim 5 , wherein the substrate has a first conductivity type,
the channel region has a second conductivity type, and
the device isolation region has the first conductivity type and is electrically connected to the substrate.
11 . The semiconductor device of claim 10 , further comprising a gate contact region formed on the gate region,
wherein the gate region and the gate contact region have the first conductivity type, and
the gate contact region and the device isolation region are electrically connected to a gate terminal.
12 . The semiconductor device of claim 5 , further comprising:
a drain contact region formed on the drain region;
a gate contact region formed on the gate region; and
a field oxide layer formed between the drain contact region and the gate contact region.
13 . The semiconductor device of claim 12 , further comprising a drift region formed between the channel region and the field oxide layer, connected to the gate region, and having a same conductivity type as the gate region.
14 . The semiconductor device of claim 13 , wherein the drift region is spaced apart from the drain region by a predetermined interval.
15 . The semiconductor device of claim 13 , further comprising:
a first electrode layer formed on the field oxide layer to be adjacent to the drain contact region; and
a second electrode layer formed on the field oxide layer to be adjacent to the gate contact region,
wherein the drain contact region and the first electrode layer are electrically connected to a drain terminal, and
the gate contact region and the second electrode layer are electrically connected to a gate terminal.
16 . The semiconductor device of claim 15 , wherein the first electrode layer and the second electrode layer are made of impurity-doped polysilicon.
17 . The semiconductor device of claim 5 , further comprising a plurality of well regions formed between the substrate and the gate region and having a same conductivity type as the gate region.
18 . The semiconductor device of claim 17 , wherein the gate region has a circular ring shape surrounding the drain region, and
the plurality of well regions each has a circular ring shape, and is arranged in a concentric circle shape and spaced apart from the substrate by a predetermined interval.