Deep backside power rail cut

Inventors: Liqiao Qin (Albany, NY); Tao Li (Slingerlands, NY); Ruilong Xie (Niskayuna, NY); Jingyun Zhang (Albany, NY)

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

H10D62/118 H10D30/014 H10D30/43 H10D30/6735 H10D30/6757 H10D62/151 H10D64/017 H10D84/0135 H10D84/0149 H10D84/0188 H10D84/038 H10D84/83 H10D84/851 H10W20/427

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12690244
App. No.: 18/610,317
Granted: Jul 21, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A nanosheet semiconductor structure including a backside cut dielectric physically separating an NFET source drain region from a PFET source drain region, where a first portion of the backside cut dielectric contacts a source drain contact and a second portion of the backside cut dielectric contacts a gate.

Claims (23)

1 . A nanosheet semiconductor structure comprising:

2 . The semiconductor structure according to claim 1 , wherein the backside cut dielectric physically bifurcates a backside source drain contact.

3 . The semiconductor structure according to claim 1 , wherein the backside cut dielectric directly contacts and physically separates adjacent source drain regions.

4 . The semiconductor structure according to claim 1 , wherein a first portion of the backside cut dielectric is taller than a second portion of the backside cut dielectric.

5 . The semiconductor structure according to claim 1 , wherein a bottommost surface of the backside cut dielectric is substantially flush with bottommost surfaces of the two adjacent backside power rails.

6 . The semiconductor structure according to claim 1 , wherein a topmost surface of the backside cut dielectric is above a bottom surface of a source drain contact.

7 . The semiconductor structure according to claim 1 , wherein a bottommost surface of the gate is below a top surface of the backside cut dielectric.

8 . A nanosheet semiconductor structure comprising:

a backside cut dielectric physically separating an NFET source drain region from a PFET source drain region, wherein substantially linear sidewalls of the backside cut dielectric contact two adjacent backside power rails, a source drain contact, and a gate.

9 . The semiconductor structure according to claim 8 , wherein the backside cut dielectric physically bifurcates a backside source drain contact.

10 . The semiconductor structure according to claim 8 , wherein the backside cut dielectric directly contacts and physically separates adjacent source drain regions.

11 . The semiconductor structure according to claim 8 , wherein a first portion of the backside cut dielectric is taller than a second portion of the backside cut dielectric.

12 . The semiconductor structure according to claim 8 , wherein a bottommost surface of the backside cut dielectric is substantially flush with bottommost surfaces of the two adjacent backside power rails.

13 . The semiconductor structure according to claim 8 , wherein a topmost surface of the backside cut dielectric is above a bottom surface of a source drain contact.

14 . The semiconductor structure according to claim 8 , wherein a bottommost surface of the gate is below a top surface of the backside cut dielectric.

15 . A nanosheet semiconductor structure comprising:

a backside cut dielectric physically separating two adjacent backside power rails, wherein substantially linear sidewalls of the backside cut dielectric contact the two adjacent backside power rails, a source drain contact, and a gate, and wherein a first top surface of the backside cut dielectric contacts a bottom surface of the source drain contact and a second top surface of the backside cut dielectric contacts a bottom surface of the gate.

16 . The semiconductor structure according to claim 15 , wherein the backside cut dielectric physically bifurcates a backside source drain contact.

17 . The semiconductor structure according to claim 15 , wherein the backside cut dielectric directly contacts and physically separates adjacent source drain regions.

18 . The semiconductor structure according to claim 15 , wherein a height of the first top surface of the backside cut dielectric measured from a bottom surface of the backside cut dielectric is larger than a height of the second top surface of the backside cut dielectric measured from the bottom surface of the backside cut dielectric.

19 . The semiconductor structure according to claim 15 , wherein a bottommost surface of the backside cut dielectric is substantially flush with bottommost surfaces of the two adjacent backside power rails.

20 . The semiconductor structure according to claim 15 , wherein a topmost surface of the backside cut dielectric is above a bottom surface of a source drain contact, and wherein a bottommost surface of the gate is below a top surface of the backside cut dielectric.