Semiconductor contact area matching

1 . A method comprising:

forming a plurality of semiconductor layers and sacrificial layers alternately in a semiconductor structure;

forming a first set of trenches in the semiconductor structure;

forming a second set of trenches in the semiconductor structure;

depositing inner spacers on opposite sides of a trench of the second set of trenches; and

forming a source/drain region,

growing a placeholder in the second set of trenches;

growing the source/drain region over the placeholder; and

forming a backside contact region;

removing the placeholder to extend the backside contact region; and

wherein the inner spacers control a size of a backside contact area of the source/drain region,

wherein the size of the backside contact area matches a size of a frontside contact area of the source/drain region.

2 . The method of claim 1 , wherein the plurality of semiconductor layers and sacrificial layers semiconductor structure include:

a first semiconductor layer,

a first sacrificial layer disposed on the first semiconductor layer,

a second semiconductor layer disposed on the first sacrificial layer,

a second sacrificial layer disposed on the second semiconductor layer,

a third semiconductor layer disposed on the second sacrificial layer,

a third sacrificial layer disposed on the third semiconductor layer,

a fourth semiconductor layer disposed on the third sacrificial layer,

a fourth sacrificial layer disposed on the fourth semiconductor layer, and

a fifth semiconductor layer disposed on the fourth sacrificial layer.

3 . The method of claim 2 , wherein forming the source/drain region further comprises:

growing a placeholder in the second set of trenches;

growing the source/drain region over the placeholder; and

depositing an interlayer dielectric over the source/drain region.

4 . The method of claim 3 , wherein forming the first set of trenches forms a fin structure, and wherein forming the first set of trenches comprises:

depositing sidewall spacers to opposite faces of the fin structure;

depositing a shallow trench isolation material in the first set of trenches;

depositing a dummy gate material over the shallow trench isolation material and the fin structure; and

depositing spacers on opposite faces of the dummy gate material.

5 . The method of claim 4 , further comprising:

removing the dummy gate material;

removing the sidewall spacers;

removing a portion of the second sacrificial layer between the sidewall spacers;

removing a portion of the third sacrificial layer between the sidewall spacers;

removing a portion of the fourth sacrificial layer between the sidewall spacers;

depositing high-k metal gate material in a space left by the removal of the dummy gate material, the sidewall spacers, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer; and

forming a gate cut through the high-k metal gate material.

6 . The method of claim 5 , further comprising:

disposing a gate contact on the high-k metal gate material;

disposing a source/drain contact on a frontside of the source/drain region;

disposing a back-end-of-line interconnect on the gate contact, the source/drain contact, and another interlayer dielectric; and

bonding the semiconductor structure to a carrier wafer, wherein the carrier wafer is bonded to the back-end-of-line interconnect.

7 . The method of claim 6 , further comprising:

removing the first semiconductor layer of the semiconductor structure;

removing the first sacrificial layer of the semiconductor structure;

removing a portion of the second semiconductor layer to expose the high-k metal gate material;

removing a portion of the exposed high-k metal gate material to form a cavity; and

filling the cavity with an inner spacer material.

8 . The method of claim 7 , further comprising:

depositing a backside interlayer dielectric on a backside of the placeholder and the inner spacer material;

forming a backside contact region;

removing the placeholder to extend the backside contact region, wherein the backside contact region extends from a backside of the source/drain region to an end of the backside contact region; and

disposing a backside metal contact on the backside of the source/drain region.

9 . The method of claim 2 , wherein the first set of trenches extend from the second semiconductor layer to the fifth semiconductor layer, and wherein the second set of trenches extend from the second semiconductor layer to the fifth semiconductor layer.

10 . The method of claim 4 , wherein the sidewall spacers extend from the second semiconductor layer to the fifth semiconductor layer.