Method of forming nanosheet field effect transistors with partial inside spacers

1 . A method of forming a nanosheet device, the method comprising:

providing a patterned channel stack extending horizontally in a first direction, the patterned channel stack comprising a plurality of nanosheet channel layers and a plurality of sacrificial release layers;

forming a dummy gate over the patterned channel stack, the dummy gate extending horizontally in a second direction perpendicular to the first direction;

forming a sidewall spacer on the dummy gate, wherein:

the dummy gate and the sidewall spacer are disposed over the patterned channel stack and define a first portion of the patterned channel stack therebelow, and

second and third portions of the patterned channel stack are disposed:

adjacent to and on opposite sides of the first portion of the patterned channel stack; and

extending outside a boundary defined by the sidewall spacer; and

recessing the plurality of sacrificial release layers with respect to the plurality of nanosheet channel layers in the second portion and the third portion of the patterned channel stack.

2 . The method of claim 1 , wherein recessing the plurality of sacrificial release layers in the second portion and the third portion forms recesses in the plurality of sacrificial release layers extending into the first portion of the patterned channel stack from the second portion and the third portions of the patterned channel stack, but not extending through the first portion of the patterned channel stack.

3 . The method of claim 1 , further comprising:

subsequent to recessing the plurality of sacrificial release layers to form recesses, forming an inner spacer layer in the recesses.

4 . The method of claim 3 , further comprising:

subsequent to forming the inner spacer layer, removing, by use of an anisotropic etch process, the second portion and the third portion of the patterned channel stack and the inner spacer layer formed in the recesses.

5 . The method of claim 4 , further comprising:

removing the dummy gate.

6 . The method of claim 5 , wherein, subsequent to removing the second portion and the third portion, the inner spacer layer remaining in the first portion comprises four cavity fills disposed between a first nanosheet channel layer and a second nanosheet channel layer, and the method further comprises:

removing remaining portions of the sacrificial release layers from between the four cavity fills.

7 . The method of claim 6 , wherein the four cavity fills comprise a silicon nitride.

8 . The method of claim 6 , wherein the four cavity fills comprise a high-k metal oxide.

9 . The method of claim 6 , further comprising:

subsequent to removing remaining portions of the sacrificial release layers, forming a gate dielectric layer on the plurality of nanosheet channel layers; and

forming a work function layer on the gate dielectric layer.

10 . The method of claim 1 , further comprising:

prior to forming the dummy gate, forming a stack cover layer over the patterned channel stack.

11 . The method of claim 10 , further comprising:

prior to recessing the plurality of sacrificial release layers, removing portions of the stack cover layer formed over the second portion and the third portion of the patterned channel stack.

12 . A method of forming a nanosheet device, the method comprising:

providing a patterned channel stack extending in a first horizontal direction, the patterned channel stack comprising a plurality of nanosheet channel layers and a plurality of sacrificial release layers;

forming a dummy gate over the patterned channel stack, the dummy gate extending in a second horizontal direction perpendicular to the first horizontal direction;

forming a sidewall spacer on the dummy gate, wherein:

the dummy gate and the sidewall spacer are disposed over the patterned channel stack and define a first portion of the patterned channel stack therebelow;

second and third portions of the patterned channel stack are disposed:

adjacent to and on opposite sides of the first portion of the patterned channel stack; and

extending outside a boundary defined by the sidewall spacer; and

the second and third portions of the patterned channel stack extend beyond outer surfaces of the sidewall spacer in the first horizontal direction;

recessing the plurality of sacrificial release layers with respect to the plurality of nanosheet channel layers in the second portion and the third portion of the patterned channel stack; and

subsequent to recessing the plurality of sacrificial release layers, removing remaining portions of the patterned channel stack that extend beyond the outer surfaces of the sidewall spacer.

13 . The method of claim 12 , further comprising:

subsequent to recessing the plurality of sacrificial release layers to form recesses, forming an inner spacer layer in the recesses.

14 . The method of claim 13 , further comprising:

removing the dummy gate.

15 . The method of claim 14 , wherein, subsequent to removing the second portion and the third portion, the inner spacer layer remaining in the first portion forms four cavity fills disposed between respective corners of a first nanosheet channel layer and a second nanosheet disposed over the first nanosheet channel layer, and the method further comprises:

removing remaining portions of a sacrificial release layers from between the four cavity fills.

16 . The method of claim 15 , wherein the four cavity fills comprise a silicon nitride.

17 . The method of claim 15 , wherein the four cavity fills comprise a high-k metal oxide.

18 . The method of claim 15 , further comprising:

subsequent to removing remaining portions of the sacrificial release layers, forming a gate dielectric layer on the plurality of nanosheet channel layers; and

forming a work function layer on the gate dielectric layer.

19 . The method of claim 12 , further comprising:

prior to forming the dummy gate, forming a stack cover layer over the patterned channel stack.

20 . The method of claim 19 , further comprising:

prior to recessing the plurality of sacrificial release layers, removing portions of the stack cover layer that extend beyond the outer surfaces of the sidewall spacer in the first horizontal direction.

21 . A method of forming a nanosheet device, the method comprising:

forming a gate dielectric layer on a plurality of nanosheet layers, the plurality of nanosheet layers comprising:

a first nanosheet channel layer and a second nanosheet channel layer each comprising a first end connected to a first source/drain region and a second end connected to a second source/drain region;

a first pair of cavity fills separating the first end of the first nanosheet channel layer from the first end of the second nanosheet channel layer; and

a second pair of cavity fills separating the second end of the first nanosheet channel layer from the second end of the second nanosheet channel layer, wherein:

the first pair of cavity fills are disposed between corners of the respective first ends of the first and second nanosheet channel layers;

the second pair of cavity fills are disposed between corners of the respective second ends of the first and second nanosheet channel layers; and

the gate dielectric layer is formed on (i) the first and second nanosheet channel layers, (ii) the first and second pairs of cavity fills, (iii) a portion of the first source/drain region between the first pair of cavity fills, and (iv) a portion of the second source/drain region between the second pair of cavity fills; and

forming a work function layer on the gate dielectric layer.