IP Library › Granted Patent US 12690252
Granted Patent B2
US 12690252 · App. 17/646,305 · Granted Jul 21, 2026

Transistor gate structure with insulating layer and method of fabrication therefor

Inventor: Darrell Glenn Hill (Chandler, AZ)
Assignee: NXP USA, INC.
H10D64/111H10D30/015H10D30/475H10D30/4755H10D64/01H10D64/685H10D64/691H10D64/693
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Quick Facts
Patent No.
US 12690252
App. No.
17/646,305
Granted
Jul 21, 2026
Kind
B2
Abstract

A transistor device includes a semiconductor substrate and a gate structure formed at the upper surface of the substrate. The gate structure includes a metal gate electrode and a gate insulating layer overlying the metal gate electrode, where edges of the gate insulating layer correspond to edges of the metal gate electrode. The transistor device also includes a first dielectric layer formed over the gate structure, and a first interconnect metal layer formed over the first dielectric layer. A portion of the first interconnect metal layer forms a field plate proximate to the gate structure, and a portion of the gate insulating layer and a portion of the first dielectric layer are present between the gate electrode and the field plate.

Claims (51)

1 . A transistor device comprising:

a semiconductor substrate that includes an upper surface;

a first dielectric layer formed on the upper surface of the semiconductor substrate;

a gate structure formed at the upper surface of the substrate, wherein the gate structure includes a metal gate electrode and a gate insulating layer overlying and in direct contact with the metal gate electrode, wherein the metal gate electrode is formed from a metal selected from a group consisting of titanium and aluminum, and wherein the metal gate electrode includes a vertical stem that extends through the first dielectric layer and a wider portion in contact with and extending above an upper surface of the first dielectric layer, wherein the gate insulating layer is formed from a dielectric material selected from a group consisting of titanium oxide and aluminum oxide, wherein the gate insulating layer is an oxidized portion of the bulk metal, and wherein edges of the gate insulating layer correspond to edges of the gate structure;

a second dielectric layer formed over the gate structure; and

a first interconnect metal layer formed over the second dielectric layer, wherein a portion of the first interconnect metal layer forms a field plate proximate to the gate structure, wherein a portion of the gate insulating layer and a portion of the second dielectric layer are present between the metal gate electrode and the field plate, and wherein the gate insulating layer covers an entire surface of the metal gate electrode between the metal gate electrode and the field plate.

2 . The transistor device of claim 1 , wherein the gate insulating layer and the second dielectric layer are distinct layers.

3 . The transistor device of claim 2 , wherein the gate insulating layer and the second dielectric layer are formed from different dielectric materials.

4 . The transistor device of claim 1 , wherein:

the gate insulating layer has a thickness in a range of 500 angstroms to 10,000 angstroms; and

the first dielectric layer has a thickness in a range of 100 angstroms to 10,000 angstroms.

5 . The transistor device of claim 1 , further comprising:

a first current-carrying electrode at the upper surface of the substrate proximate to a first side of the gate structure; and

a second current-carrying electrode at the upper surface of the substrate proximate to a second side of the gate structure.

6 . The transistor device of claim 5 , wherein the transistor device is a high electron mobility transistor.

7 . The transistor device of claim 1 , wherein:

the metal gate electrode is formed from titanium; and

the gate insulating layer is formed from titanium oxide.

8 . The transistor device of claim 1 , wherein:

the metal gate electrode is formed from aluminum; and

the gate insulating layer is formed from aluminum oxide.

9 . A field effect transistor comprising:

a semiconductor substrate that includes an upper surface and a channel below the upper surface;

a source electrode formed at the upper surface of the substrate over the channel;

a drain electrode formed at the upper surface of the substrate over the channel;

a first dielectric layer formed on the upper surface of the semiconductor substrate;

a gate structure formed at the upper surface of the substrate, wherein the gate structure includes a metal gate electrode and a gate insulating layer overlying and in direct contact with the metal gate electrode, wherein the metal gate electrode is formed from a metal selected from a group consisting of titanium and aluminum, and wherein the metal gate electrode includes a vertical stem that extends through the first dielectric layer and a wider portion in contact with and extending above an upper surface of the first dielectric layer, wherein the gate insulating layer is formed from a dielectric material selected from a group consisting of titanium oxide and aluminum oxide, wherein the gate insulating layer is an oxidized portion of the bulk metal, and wherein edges of the gate insulating layer correspond to edges of the gate structure;

a second dielectric layer formed over the gate structure; and

a first interconnect metal layer formed over the second dielectric layer, wherein a portion of the first interconnect metal layer forms a field plate proximate to the gate structure, wherein a portion of the gate insulating layer and a portion of the second dielectric layer are present between the metal gate electrode and the field plate, and wherein the gate insulating layer covers an entire surface of the metal gate electrode between the metal gate electrode and the field plate.

10 . The field effect transistor device of claim 9 , wherein the gate insulating layer and the second dielectric layer are distinct layers.

11 . The field effect transistor device of claim 9 , wherein the field effect transistor is a high electron mobility transistor.

12 . The field effect transistor device of claim 9 , wherein:

the metal gate electrode is formed from titanium; and

the gate insulating layer is formed from titanium oxide.

13 . The field effect transistor device of claim 9 , wherein:

the metal gate electrode is formed from aluminum; and

the gate insulating layer is formed from aluminum oxide.

14 . A method of fabricating a transistor device, the method comprising:

providing a substrate that includes an upper surface;

forming a first dielectric layer on the upper surface of the semiconductor substrate;

forming a gate structure at the upper surface of the substrate, wherein forming the gate structure includes

forming a metal gate electrode at the upper surface of the substrate, wherein the metal gate electrode is formed from a metal selected from a group consisting of titanium and aluminum, and wherein the metal gate electrode includes a vertical stem that extends through the first dielectric layer and a wider portion in contact with and extending above an upper surface of the first dielectric layer, and

oxidizing the bulk metal of the metal gate electrode to form a gate insulating layer over and in direct contact with the metal gate electrode, wherein the gate insulating layer is formed from a dielectric material selected from a group consisting of titanium oxide and aluminum oxide, and wherein edges of the gate insulating layer correspond to edges of the gate structure;

depositing a second dielectric layer over the gate structure; and

forming a first interconnect metal layer over the second dielectric layer, wherein a portion of the first interconnect metal layer forms a field plate proximate to the gate structure, wherein a portion of the gate insulating layer and a portion of the second dielectric layer are present between the metal gate electrode and the field plate, and wherein the gate insulating layer covers an entire surface of the metal gate electrode between the metal gate electrode and the field plate.

15 . The method of claim 14 , wherein:

forming the metal gate electrode comprises forming the metal gate electrode from titanium as the bulk metal; and

oxidizing the bulk metal to form the gate insulating layer comprises oxidizing the titanium to form the gate insulating layer as a titanium oxide layer.

16 . The method of claim 14 , wherein:

forming the metal gate electrode comprises forming the metal gate electrode from aluminum as the bulk metal; and

oxidizing the bulk metal to form the gate insulating layer comprises oxidizing the aluminum to form the gate insulating layer as an aluminum oxide layer.