Metal pillar connection topologies for heterogeneous packaging
A radio frequency (“RF”) transistor amplifier die includes a semiconductor layer structure having a plurality of transistor cells, and an insulating layer on a surface of the semiconductor layer structure. Conductive pillar structures protrude from the insulating layer opposite the surface of the semiconductor layer structure, and are configured to provide input signal, output signal, or ground connections to the transistor cells. The ground connections are arranged between the input and/or output signal connections to the transistor cells. Related devices and packages are also discussed.
1 . A radio frequency (“RF”) transistor amplifier die, comprising:
a semiconductor layer structure including an active region comprising a plurality of transistor cells, wherein the transistor cells comprise gate fingers extending on the active region of the semiconductor layer structure;
an insulating layer on a surface of the semiconductor layer structure; and
a plurality of conductive pillar structures that protrude from a surface of the insulating layer opposite the surface of the semiconductor layer structure,
wherein a first subset of the conductive pillar structures is configured to provide ground connections to the transistor cells, a second subset of the conductive pillar structures is configured to provide input signal connections to the transistor cells, and respective conductive pillar structures of the second subset are arranged in the active region, are coupled to the gate fingers between opposing ends thereof by one or more intervening metal layers thereon, and are configured to be attached to at least one device that is external to the RF transistor amplifier die.
2 . The RF transistor amplifier die of claim 1 , wherein a third subset of the conductive pillar structures is configured to provide output signal connections to the transistor cells, and respective conductive pillar structures of the first subset are arranged between the respective conductive pillar structures of the second and third subsets that are configured to provide the input signal and output signal connections, respectively.
3 . The RF transistor amplifier die of claim 1 , wherein the respective conductive pillar structures of the second subset are arranged between respective conductive pillar structures of the first subset.
4 . The RF transistor amplifier die of claim 3 , wherein a third subset of the conductive pillar structures is configured to provide output signal connections to the transistor cells, and respective conductive pillar structures of the third subset are arranged between respective conductive pillar structures of the first subset.
5 . The RF transistor amplifier die of claim 3 , wherein the transistor cells comprise drain and source fingers extending on the semiconductor layer structure, wherein a third subset of the conductive pillar structures is configured to provide output signal connections to the transistor cells, wherein the respective conductive pillar structures of the first subset are coupled to the source fingers, and the respective conductive pillar structures of the third subset are on the drain fingers.
6 . The RF transistor amplifier die of claim 5 , wherein the respective conductive pillar structures of the second subset are between opposing ends of the gate fingers.
7 . The RF transistor amplifier die of claim 5 , wherein the respective conductive pillar structures of the first subset are coupled to respective extension regions of the source fingers, and the respective conductive pillar structures of the second subset are coupled to respective extension regions of the gate fingers.
8 . The RF transistor amplifier die of claim 7 , wherein the gate, drain, and/or source fingers respectively comprise finger segments that are spaced apart from each other, and wherein the respective extension regions are arranged between the finger segments.
9 . The RF transistor amplifier die of claim 1 , wherein the transistor cells comprise drain and source fingers extending on the semiconductor layer structure, and wherein the input signal connections provided by the respective conductive pillar structures of the second subset are free of wirebond connection pads that electrically connect to the gate fingers.
10 . The RF transistor amplifier die of claim 9 , wherein at least one of the respective conductive pillar structures of the second subset is coupled to multiple of the gate fingers by the one or more intervening metal layers thereon.
11 . The RF transistor amplifier die of claim 1 , wherein the conductive pillar structures protrude from the insulating layer adjacent a top of the RF transistor amplifier die, and further comprising:
a substrate on the semiconductor layer structure opposite the surface having the insulating layer thereon; and
conductive via structures that extend through the substrate, wherein the conductive via structures are configured to provide at least one of other input signal, output signal, and ground connections to the transistor cells, respectively.
12 . The RF transistor amplifier die of claim 1 , wherein the conductive pillar structures of the first and third subsets are arranged within an active region comprising the transistor cells to provide the ground and output signal connections, respectively.
13 . The RF transistor amplifier die of claim 1 , wherein the respective conductive pillar structures of the second subset and the one or more intervening metal layers between the respective conductive pillar structures of the second subset and the gate fingers are wider than the gate fingers.
14 . A radio frequency (“RF”) transistor amplifier die, comprising:
a semiconductor layer structure including an active region comprising a plurality of transistor cells;
an insulating layer on a surface of the semiconductor layer structure; and
a plurality of conductive pillar structures that protrude from a surface of the insulating layer opposite the surface of the semiconductor layer structure, wherein a first subset of the plurality of conductive pillar structures is configured to provide input signal connections to the transistor cells,
wherein the transistor cells comprise gate fingers extending on the active region of the semiconductor layer structure, and wherein respective conductive pillar structures of the first subset are arranged in the active region, are coupled to the gate fingers between opposing ends thereof by one or more intervening metal layers thereon, and are configured to be attached to at least one device that is external to the RF transistor amplifier die.
15 . The RF transistor amplifier die of claim 14 , wherein a second subset and a third subset of the plurality of conductive pillar structures are configured to provide ground connections and output signal connections to the transistor cells, respectively, and respective conductive pillar structures of the second subset are arranged between respective conductive pillar structures of the first subset and respective conductive pillar structures of the third subset.
16 . The RF transistor amplifier die of claim 14 , wherein a second subset of the plurality of conductive pillar structures is configured to provide ground connections to the transistor cells, and respective conductive pillar structures of the first subset are arranged between respective conductive pillar structures of the second subset.
17 . The RF transistor amplifier die of claim 16 , wherein a third subset of the plurality of conductive pillar structures is configured to provide output signal connections to the transistor cells, and respective conductive pillar structures of the third subset are arranged between respective conductive pillar structures of the second subset.
18 . The RF transistor amplifier die of claim 17 , wherein the transistor cells further comprise source and drain fingers extending on the semiconductor layer structure, wherein the respective conductive pillar structures of the second subset are between opposing ends of the source fingers, and/or the respective conductive pillar structures of the third subset are between opposing ends of the drain fingers.
19 . A radio frequency (“RF”) transistor amplifier die, comprising:
a semiconductor layer structure including an active region comprising a plurality of transistor cells adjacent a surface thereof; and
a plurality of conductive pillar structures that protrude away from the surface of the semiconductor layer structure, wherein a first subset of the plurality of conductive pillar structures are configured to provide input signal connections to the transistor cells,
wherein the transistor cells comprise gate, drain, and source fingers extending on the active region of the semiconductor layer structure, and wherein respective conductive pillar structures of the first subset are arranged in the active region, are coupled to the gate fingers by one or more intervening metal layers thereon, and are configured to be attached to at least one device that is external to the RF transistor amplifier die and provide the input signal connections free of connecting buses that electrically connect the gate fingers.
20 . The RF transistor amplifier die of claim 19 , wherein respective conductive pillar structures of a second subset of the plurality of conductive pillar structures are coupled to the source fingers between opposing ends thereof, the respective conductive pillar structures of the first subset are coupled to the gate fingers between opposing ends thereof, and/or respective conductive pillar structures of a third subset of the plurality of conductive pillar structures are coupled to the drain fingers between opposing ends thereof.
21 . The RF transistor amplifier die of claim 19 , wherein a second subset and a third subset of the plurality of conductive pillar structures are configured to provide ground connections and output signal connections to the transistor cells, respectively, and respective conductive pillar structures of the second subset are arranged between respective conductive pillar structures of the first and/or third subsets.
22 . The RF transistor amplifier die of claim 21 , wherein the respective conductive pillar structures of the second subset that are configured to provide the ground connections are arranged between the respective conductive pillar structures of the first subset and the respective conductive pillar structures of the third subset that are configured to provide the input signal and output signal connections, respectively.
23 . An integrated circuit device package, comprising:
a radio frequency (“RF”) transistor amplifier die comprising a semiconductor layer structure including an active region comprising a plurality of transistor cells, an insulating layer on a surface of the semiconductor layer structure, and a plurality of conductive pillar structures that protrude from a surface of the insulating layer opposite the surface of the semiconductor layer structure; and
a package substrate comprising conductive connection patterns corresponding to an arrangement of the conductive pillar structures, wherein the conductive pillar structures attach the RF transistor amplifier die to the conductive connection patterns of the package substrate, which are external to the RF transistor amplifier die, and are configured to provide at least one of input signal, output signal, and ground connections to the transistor cells,
wherein the transistor cells comprise gate fingers extending on the active region of the semiconductor layer structure, a first subset of the conductive pillar structures are configured to provide the input signal connections, and respective conductive pillars of the first subset are arranged in the active region and are coupled to the gate fingers between opposing ends thereof by one or more intervening metal layers thereon.
24 . The integrated circuit device package of claim 23 , wherein the conductive pillar structures protrude from the insulating layer adjacent a top of the RF transistor amplifier die, and wherein the RF transistor amplifier die further comprises:
a substrate on the semiconductor layer structure opposite the surface having the insulating layer thereon; and
conductive via structures that extend through the substrate, wherein the conductive via structures are configured to provide at least one of other input signal, output signal, or ground connections to the transistor cells, respectively.
25 . The integrated circuit device package of claim 23 , wherein the input signal connections provided by the conductive pillar structures are free of wirebond connection pads that electrically connect to the gate fingers of the transistor cells.
26 . The integrated circuit device package of claim 23 , wherein the semiconductor layer structure comprises one or more epitaxial layers of a wide bandgap semiconductor material.
27 . The integrated circuit device package of claim 23 , wherein the semiconductor layer structure comprises a Group-III nitride material on a silicon carbide substrate.