Semiconductor device sidewall of the gate semiconductor layer including a plurality of surfaces having different slopes
A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.
1 . A semiconductor device comprising:
a channel layer;
a barrier layer on the channel layer, an energy band gap of the barrier layer being greater than an energy band gap of the channel layer;
a gate electrode on the barrier layer;
a gate semiconductor layer between the barrier layer and the gate electrode; and
a source and a drain on the channel layer and spaced apart from each other, wherein
the gate semiconductor layer includes a first surface contacting the barrier layer, a second surface contacting the gate electrode and a first sidewall connecting the first surface with the second surface and a second sidewall opposite the first sidewall,
an area of the second surface of the gate semiconductor layer is narrower than an area of the first surface of the gate semiconductor layer, and
the first sidewall and the second sidewall of the gate semiconductor layer each includes a plurality of surfaces having different slopes,
wherein the plurality of surfaces includes a first inclined surface contacting the barrier layer and a second inclined surface extending between the second surface and the first inclined surface and contacting the gate electrode, the second inclined surface being nonparallel with the second surface and an angle between the first inclined surface and the first surface is less than an angle between the second inclined surface and the second surface.
2 . The semiconductor device of claim 1 , wherein
the first inclined surface contacts the first surface of the gate semiconductor layer at a first angle, and
the second inclined surface contacts the second surface of the gate semiconductor layer at a second angle, and
the first angle is less than the second angle.
3 . The semiconductor device of claim 2 , wherein the first angle is about 40° or less.
4 . The semiconductor device of claim 2 , wherein the second angle is greater than or equal to about 60° and less than or equal to about 90°.
5 . The semiconductor device of claim 1 , wherein
angles formed by the plurality of surfaces and the first surface decrease as positions of the plurality of surfaces approach the first surface.
6 . The semiconductor device of claim 1 , wherein
the first surface of the gate semiconductor layer and the second surface of the gate semiconductor layer are apart from each other in a height direction, and in the height direction, a height of the first sidewall of the gate semiconductor layer is greater than or equal to about 2 nm and less than or equal to about 200 nm.
7 . The semiconductor device of claim 1 , wherein
the first surface of the gate semiconductor layer and the second surface of the gate semiconductor layer are apart from each other in a height direction, and
in the height direction, a height of each of the plurality of surfaces is greater than or equal to about 1 nm and less than or equal to about 100 nm.
8 . The semiconductor device of claim 1 , wherein at least one of the plurality of surfaces comprises a curved surface.
9 . The semiconductor device of claim 1 , wherein the plurality of surfaces form a concave curved surface.
10 . The semiconductor device of claim 1 , wherein the channel layer comprises a group III-V compound semiconductor.
11 . The semiconductor device of claim 1 , wherein the gate semiconductor layer comprises p-type GaN.
12 . The semiconductor device of claim 1 , wherein
the semiconductor device comprises a high electron mobility transistor (HEMT) having a normally off property.
13 . A method of manufacturing a semiconductor device, the method comprising:
sequentially forming a channel layer, a barrier layer, and a gate semiconductor layer on a substrate;
etching the gate semiconductor layer to have a shape in which an area of a first surface of the gate semiconductor layer is wider than an area of a second surface of the gate semiconductor layer, the first surface of the gate semiconductor layer being in contact with the barrier layer, the second surface of the gate semiconductor layer being opposite the first surface of the gate semiconductor layer, the gate semiconductor layer including a first sidewall connecting the first surface of the gate semiconductor layer to the second surface of the gate semiconductor layer and a second sidewall opposite the first sidewall connecting the first surface of the gate semiconductor layer to the second surface of the gate semiconductor laver,
the etching the gate semiconductor layer including forming a plurality of surfaces having different slopes in each of the first sidewall and the second sidewall of the gate semiconductor layer;
forming a gate electrode on the gate semiconductor layer; and
forming a source and a drain in contact with a first side of the channel layer and a second side of the channel layer, respectively,
wherein the plurality of surfaces includes a first inclined surface contacting the barrier layer and a second inclined surface extending between the second surface and the first inclined surface and contacting the gate electrode, the second inclined surface being nonparallel with the second surface and an angle between the first inclined surface and the first surface is less than an angle between the second inclined surface and the second surface.
14 . The method of claim 13 , wherein, in the etching the gate semiconductor layer, an angle formed by each of the plurality of surfaces and the first surface decreases as positions of the plurality of surfaces approach the first surface.
15 . The method of claim 13 , wherein
the first inclined surface contacts the first surface of the gate semiconductor layer at a first angle, and
the second inclined surface contacts the second surface of the gate semiconductor layer at a second angle, and
the first angle is less than the second angle.
16 . The method of claim 15 , wherein the etching the gate semiconductor layer comprises:
forming the second inclined surface using a first gas; and
forming the first inclined surface using a second gas, the second gas being different from the first gas.
17 . The method of claim 13 , wherein the etching the gate semiconductor layer is performed after the forming the gate electrode.
18 . The method of claim 13 , wherein the forming the gate electrode is performed after the etching the gate semiconductor layer.
19 . The method of claim 13 , wherein a material of the barrier layer has a greater energy band gap than an energy band gap of a material of the channel layer.
20 . The semiconductor device of claim 1 , wherein the source and the drain are in ohmic contact with the channel layer.