IP Library Granted Patent US 12690256
Granted Patent B2
US 12690256 · App. 18/380,930 · Granted Jul 21, 2026

Semiconductor device with capping layer and method for fabricating the same

Inventor: Tse-Yao Huang (Taipei City, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10D64/66H10D64/01H10D64/0113H10D64/01306H10D64/01312H10D64/01314H10D64/661H10D64/664H10P14/418H10W20/056H10W20/077H10W20/4451H10W20/48H10W74/134H10W74/43H10D64/513H10W20/081H10W20/4462
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690256
App. No.
18/380,930
Granted
Jul 21, 2026
Kind
B2
Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and having a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer comprises germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

Claims (20)

1 . A method for fabricating a semiconductor device, comprising:

providing a substrate;

forming a capping mask layer on the substrate;

forming a first trench along the capping mask layer and extending to the substrate;

conformally forming a layer of first insulating material into the first trench;

forming a first work function layer on the layer of first insulating material and in the first trench;

forming a first conductive layer on the first work function layer and in the first trench; and

forming a first capping layer on the first conductive layer;

wherein the first capping layer comprises germanium oxide;

wherein the first conductive layer comprises germanium;

wherein the first work function layer comprises silicon and/or germanium with substantially no oxygen and nitrogen;

wherein the first gate insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, a high-k material, or a combination thereof;

wherein the capping mask layer comprises silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, silicon nitride oxide, or a combination thereof;

wherein forming the first capping layer on the first conductive layer comprises:

alternately and sequentially introducing a germanium precursor and an oxygen source to form a layer of first capping material filling the first trench; and

performing a planarization process until a top surface of the capping mask layer is exposed to turn the layer of first capping material into the first capping layer.

2 . The method for fabricating the semiconductor device of claim 1 , wherein the germanium precursor comprises germanium ethoxide or tetrakis (dimethylamino) germanium.

3 . The method for fabricating the semiconductor device of claim 2 , wherein the oxygen source comprises an activated or excited oxygen species.

4 . The method for fabricating the semiconductor device of claim 3 , wherein a process temperature of forming the first capping layer is between about 20° C. and about 600° C.

5 . The method for fabricating the semiconductor device of claim 4 , wherein the planarization process comprises an etching process, a chemical mechanical polishing process, or a combination thereof.