Dipole patterning for CMOS devices

1 . A semiconductor device, comprising:

a substrate;

first and second n-type transistors over the substrate;

first and second p-type transistors over the substrate,

wherein the first n-type transistor includes a first stack of channel layers and a first portion of a high-k dielectric layer surrounding channel layers of the first stack of channel layers,

wherein the second n-type transistor includes a second stack of channel layers, a second portion of the high-k dielectric layer surrounding channel layers of the second stack of channel layers, and an n-type dipole layer over the second portion of the high-k dielectric layer, wherein the second portion of the high-k dielectric layer includes a higher amount of an n-type dipole material than the first portion of the high-k dielectric layer,

wherein the first p-type transistor includes a third stack of channel layers and a third portion of the high-k dielectric layer surrounding channel layers of the third stack of channel layers, and

wherein the second p-type transistor includes a fourth stack of channel layers, a fourth portion of the high-k dielectric layer surrounding channel layers of the fourth stack of channel layers, and a p-type dipole layer over the fourth portion of the high-k dielectric layer, wherein the fourth portion of the high-k dielectric layer includes a higher amount of a p-type dipole material than the third portion of the high-k dielectric layer; and

a metal stack over and directly interfacing with the first portion of the high-k dielectric layer, the n-type dipole layer, the third portion of the high-k dielectric layer, and the p-type dipole layer.

2 . The semiconductor device of claim 1 , wherein the n-type dipole material includes one of lanthanum, yttrium, and strontium.

3 . The semiconductor device of claim 1 , wherein the p-type dipole material includes one of aluminum, titanium, niobium, and scandium.

4 . The semiconductor device of claim 1 , further comprising:

a first interfacial layer between the first stack of channel layers and the first portion of the high-k dielectric layer;

a second interfacial layer between the second stack of channel layers and the second portion of the high-k dielectric layer;

a third interfacial layer between the third stack of channel layers and the third portion of the high-k dielectric layer; and

a fourth interfacial layer between the fourth stack of channel layers and the fourth portion of the high-k dielectric layer.

5 . The semiconductor device of claim 4 ,

wherein the second interfacial layer includes a higher amount of an n-type dipole material than the first interfacial layer,

wherein the fourth interfacial layer includes a higher amount of a p-type dipole material than the third interfacial layer.

6 . The semiconductor device of claim 1 , wherein the metal stack includes:

an n-type work function metal layer over the first and the second portions of the high-k dielectric layer; and

a p-type work function metal layer over the third and fourth portions of the high-k dielectric layer.

7 . The semiconductor device of claim 6 , wherein the n-type work function metal layer includes titanium, aluminum, carbon, or combinations thereof.

8 . The semiconductor device of claim 6 , wherein the p-type work function metal layer includes titanium nitride, tantalum nitride, tungsten nitride, ruthenium, or combinations thereof.

9 . The semiconductor device of claim 6 , wherein the n-type work function metal layer directly contacts the second portion of the high-k dielectric layer, and the p-type work function metal layer directly contacts the fourth portion of the high-k dielectric layer.

10 . A semiconductor device, comprising:

a substrate;

first and second n-type transistors over the substrate; and

first and second p-type transistors over the substrate,

wherein the first n-type transistor includes a first stack of channel layers, a first portion of a high-k dielectric layer surrounding channel layers of the first stack of channel layers, and a first portion of an n-type work function metal layer over the first portion of the high-k dielectric layer,

wherein the second n-type transistor includes a second stack of channel layers, a second portion of the high-k dielectric layer surrounding channel layers of the second stack of channel layers, and a second portion of the n-type work function metal layer over the second portion of the high-k dielectric layer, wherein the second portion of the high-k dielectric layer includes a higher amount of an n-type dipole material than the first portion of the high-k dielectric layer,

wherein the first p-type transistor includes a third stack of channel layers, a third portion of the high-k dielectric layer surrounding channel layers of the third stack of channel layers, and a first portion of a p-type work function metal layer over the third portion of the high-k dielectric layer, and

wherein the second p-type transistor includes a fourth stack of channel layers, a fourth portion of the high-k dielectric layer surrounding channel layers of the fourth stack of channel layers, and a second portion of the p-type work function metal layer over the fourth portion of the high-k dielectric layer, wherein the fourth portion of the high-k dielectric layer includes a higher amount of a p-type dipole material than the third portion of the high-k dielectric layer.

11 . The semiconductor device of claim 10 ,

wherein the n-type dipole material includes one of lanthanum, yttrium, and strontium,

wherein the p-type dipole material includes one of aluminum, titanium, niobium, and scandium.

12 . The semiconductor device of claim 10 , further comprising:

a first dipole layer between the second portion of the n-type work function metal layer and the second portion of the high-k dielectric layer; and

a second dipole layer between the second portion of the p-type work function metal layer and the fourth portion of the high-k dielectric layer,

wherein the first portion of the n-type work function metal layer directly interfaces with the first portion of the high-k dielectric layer, the second portion of the n-type work function metal layer directly interfaces with the first dipole layer, the first portion of the p-type work function metal layer directly interfaces with the third portion of the high-k dielectric layer, and the second portion of the p-type work function metal layer directly interfaces with the second dipole layer.

13 . The semiconductor device of claim 12 , wherein the first dipole layer includes the n-type dipole material, and the second dipole layer includes the p-type dipole material.

14 . The semiconductor device of claim 10 , further comprising a bulk metal layer over the n-type and the p-type work function metal layers.

15 . The semiconductor device of claim 14 , wherein the bulk metal layer includes aluminum, tungsten, or copper.

16 . The semiconductor device of claim 14 , further comprising a blocking layer between the bulk metal layer and the n-type and the p-type work function metal layers.

17 . A semiconductor device, comprising:

a substrate;

first and second n-type transistors over the substrate and having first and second channel layers, respectively, wherein the first channel layer is one layer of a first stacked channel of layers, and the second channel layer is one layer of a second stacked channel of layers;

first and second p-type transistors over the substrate and having third and fourth channel layers, respectively, wherein the third channel layer is one layer of a third stacked channel of layers, and the fourth channel layer is one layer of a fourth stacked channel of layers;

interfacial layers over and interfacing with the first, the second, the third, and the fourth channel layers, respectively;

a high-k dielectric layer over and interfacing with the interfacial layers;

an n-type work function metal layer over and interfacing with the high-k dielectric layer; and

a p-type work function metal layer over and interfacing with the high-k dielectric layer,

wherein a first portion of the high-k dielectric layer includes a higher amount of a first n-type dipole material than a second portion of the high-k dielectric layer,

wherein a third portion of the high-k dielectric layer includes a higher amount of a first p-type dipole material than a fourth portion of the high-k dielectric layer.

18 . The semiconductor device of claim 17 , wherein the interfacial layers include:

a first interfacial layer between the first channel layer and the first portion of the high-k dielectric layer,

a second interfacial layer between the second channel layer and the second portion of the high-k dielectric layer

a third interfacial layer between the third channel layer and the third portion of the high-k dielectric layer; and

a fourth interfacial layer between the fourth channel layer and the fourth portion of the high-k dielectric layer.

19 . The semiconductor device of claim 18 ,

wherein the first interfacial layer includes a higher amount of a second n-type dipole material than the second interfacial layer,

wherein the third interfacial layer includes a higher amount of a second p-type dipole material than the fourth interfacial layer.

20 . The semiconductor device of claim 19 ,

wherein the first n-type dipole material is same as the second n-type dipole material,

wherein the first p-type dipole material is same as the second p-type dipole material.