Device and method of forming 3D U-shaped nanosheet cfet
A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.
1 . A semiconductor device comprising:
a substrate comprising a working surface; and
a transistor formed in the substrate, the transistor comprising:
a complex channel structure comprising a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure,
a gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and
S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.
2 . The semiconductor device of claim 1 , wherein each tail portion extends along a direction substantially perpendicular to the main direction.
3 . The semiconductor device of claim 2 , wherein the transistor comprises:
a first S-D region comprising a first one of the tail portions connected to a first end of the main portion and terminating in a first one of the S-D ends; and
a second S-D region comprising a second one of the tail portions connected to a second end of the main portion and terminating in a second one of the S-D ends.
4 . The semiconductor device of claim 1 , wherein the GAA structure comprises a high-k layer formed around the main portion and a gate metal formed around the high-k layer.
5 . The semiconductor device of claim 1 , wherein the S-D contacts comprise epitaxial doped silicon.
6 . The semiconductor device of claim 1 , wherein the S-D contacts comprise metal and silicide.
7 . The semiconductor device of claim 3 , wherein the complex channel structure is a U-shaped channel structure in a plane parallel to the working surface of the substrate and ends of the U-shaped channel structure provide the first and second S-D ends.
8 . The semiconductor device of claim 7 , comprising a plurality of said transistors each having said U-shaped channel structure and arranged adjacent to each other such that the S-D ends of a first transistor face the S-D ends of a second transistor.
9 . The semiconductor device of claim 7 , comprising a plurality of said transistors each having said U-shaped channel structure and arranged adjacent to each other such that the S-D ends of a first transistor are staggered with respect to the S-D ends of a second transistor.
10 . The semiconductor device of claim 7 , comprising a stack of transistors each having said U-shaped channel structure and arranged over each other such that the U-shaped channel structure of a lower transistor is vertically aligned with the U-shaped channel structure of an upper transistor.