Leakage reduction methods and structures thereof
A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.
1 . A method, comprising:
forming a first fin within and circumscribed by a first cell region, a second fin within and circumscribed by a second cell region, and a dummy fin at a boundary between the first cell region and the second cell region;
after forming the first fin and the second fin, depositing a first gate layer over the first fin, the second fin, and the dummy fin; and
removing a portion of the first gate layer to form a patterned first gate layer corresponding to a first mask.
2 . The method of claim 1 , further comprising:
depositing a second gate layer over the patterned first gate layer and over the first fin, the second fin, and the dummy fin; and
removing a portion of the second gate layer to form a patterned second gate layer corresponding to a second mask.
3 . The method of claim 2 , further comprising:
depositing a third gate layer over the patterned second gate layer and over the first fin, the second fin, and the dummy fin; and
removing a portion of the third gate layer to form a patterned third gate layer corresponding to a third mask.
4 . The method of claim 3 , further comprising:
depositing a fourth gate layer over the patterned third gate layer and over the first fin, the second fin, and the dummy fin; and
removing a portion of the fourth gate layer to form a patterned fourth gate layer corresponding to a fourth mask.
5 . The method of claim 4 , wherein the first mask, the second mask, the third mask, and the fourth mask compose a mask set configured to provide a target threshold voltage of the dummy fin at the boundary.
6 . The method of claim 1 , wherein the first cell region and the second cell region both include an N-type active region, or wherein the first cell region and the second cell region both include a P-type active region.
7 . The method of claim 6 , wherein the first cell region includes an N-type standard threshold voltage (NSVT) region, and wherein the second cell region includes an N-type low threshold voltage (NLVT) region.
8 . The method of claim 6 , wherein the first cell region includes an N-type standard threshold voltage (NSVT) region, and wherein the second cell region includes an N-type ultra-low threshold voltage (NULVT) region.
9 . The method of claim 6 , wherein the first cell region includes an N-type low threshold voltage (NLVT) region, and wherein the second cell region includes an N-type ultra-low threshold voltage (NULVT) region.
10 . The method of claim 6 , wherein the first cell region includes a P-type standard threshold voltage (PSVT) region, and wherein the second cell region includes a P-type low threshold voltage (PLVT) region.
11 . The method of claim 6 , wherein the first cell region includes a P-type standard threshold voltage (PSVT) region, and wherein the second cell region includes a P-type ultra-low threshold voltage (PULVT) region.
12 . The method of claim 6 , wherein the first cell region includes a P-type low threshold voltage (PLVT) region, and wherein the second cell region includes a P-type ultra-low threshold voltage (PULVT) region.
13 . A method, comprising:
providing a substrate including a first active region and a second active region that abuts the first active region at a boundary;
forming a first fin within the first active region, a second fin within the second active region, and a dummy fin at the boundary, wherein the dummy fin has a first threshold voltage; and
performing a threshold voltage implant into the dummy fin to provide an ion-implanted dummy fin having a second threshold voltage greater than the first threshold voltage.
14 . The method of claim 13 , further comprising:
forming a gate stack over the first fin, the second fin, and the ion-implanted dummy fin.
15 . The method of claim 13 , wherein the performing the threshold voltage implant includes implanting an N-type dopant including at least one of arsenic, phosphorous, and antimony.
16 . The method of claim 13 , wherein the performing the threshold voltage implant includes implanting a P-type dopant including at least one of boron, BF 2 , aluminum, gallium, and indium.
17 . A method, comprising:
depositing a silicon germanium (SiGe) layer within a recess at a cell boundary between a first cell region and a second cell region;
forming a first active fin within the first cell region, a second active fin within the second cell region, and a dummy fin within the SiGe layer at the cell boundary; and
forming a gate stack over the first active fin, the second active fin, and the dummy fin.
18 . The method of claim 17 , wherein the SiGe layer includes about 30% Ge (Si 0.7 Ge 0.3 ).
19 . The method of claim 17 , wherein the first cell region and the second cell region both include an N-type region.
20 . The method of claim 17 , wherein the forming the dummy fin within the SiGe layer at the cell boundary improves isolation between the first cell region and the second cell region.