PJ junction device structure in semiconductor device with back side power delivery network (BSPDN) structure

1 . A semiconductor device comprising:

at least one field-effect transistor in a 1 st layer including a first portion of a substrate, the 1 st layer being above a 2 nd layer that includes a second portion of the substrate;

at least one back side power delivery network (BSPDN) structure;

an interlayer dielectric (ILD) structure formed around the at least one BSPDN structure in the 2 nd layer and extending to an interface with the first portion of the substrate; and

at least one PN junction device at a lateral side of the at least one BSPDN structure in the second portion of the substrate in the 2 nd layer,

wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.

2 . A semiconductor device comprising:

at least one field-effect transistor in a 1 st layer including a first portion of a substrate; and

at least one back side power delivery network (BSPDN) structure and at least one PN junction device at a lateral side of the at least one BSPDN structure in a 2 nd layer that includes a second portion of the substrate, wherein the second layer is below the 1 st layer;

an interlayer dielectric (ILD) structure formed around the at least one BSPDN structure in the 2 nd layer and extending to an interface with the first portion of the substrate,

wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source,

wherein the semiconductor device further comprises a 1 st substrate structure at the lateral side of the at least one BSPDN structure in the 2 nd layer, and

wherein the at least one PN junction device is formed in the 1 st substrate structure.

3 . The semiconductor device of claim 1 , further comprising:

a back side contact plug in the 2 nd layer, the back side contact plug connecting one of a p-region and an n-region of the at least one PN junction device to the voltage source or another circuit element; and

a via metal pattern in the 1 st layer, the via metal pattern connecting the other of the p-region and the n-region of the at least one PN junction device to the voltage source or another circuit element.

4 . The semiconductor device of claim 1 , further comprising:

a 1 st substrate structure at the lateral side of the at least one BSPDN structure in the 2 nd layer, the at least one PN junction device being formed in the 1 st substrate structure; and

a 2 nd substrate structure based on which a channel structure of the at least one field-effect transistor is formed, the 2 nd substrate structure being formed in the 1 st layer without being extended to the 2 nd layer.

5 . The semiconductor device of claim 1 , wherein the at least one field-effect transistor comprises two field-effect transistors, and

wherein the at least one PN junction device is between the two field-effect transistors in the 2 nd layer.

6 . A method of manufacturing a semiconductor device, the method comprising:

providing at least one field-effect transistor in a 1 st layer including a first portion of a substrate, the 1 st layer being above a 2 nd layer that includes a second portion of the substrate;

forming at least one PN junction device in the substrate in the 2 nd layer;

removing the substrate in the 2 nd layer except at the second portion where the at least one PN junction device is formed in the 2 nd layer, the at least one PN junction device being formed in the second portion of the substrate;

forming an interlayer dielectric (ILD) structure in the 2 nd layer that extends to an interface with the first portion of the substrate; and

forming at least one back side power delivery network (BSPDN) structure at a lateral side of the at least one PN junction device in the 2 nd layer, the at least one BSPDN structure being formed in the ILD structure and being connected to the at least one field-effect transistor.

7 . The method of claim 6 , further comprising:

connecting the at least one BSPDN structure to the at least one PN junction device.

8 . The semiconductor device of claim 1 , further comprising a back side contact plug in the 2 nd layer, the back side contact plug connecting the at least one PN junction device to the voltage source or another circuit element,

wherein the back side contact plug is in a via hole and on a surface of the at least one PN junction device.

9 . The semiconductor device of claim 1 , further comprising a back side contact plug in the 2 nd layer,

wherein the back side contact plug is on a 2 nd surface of the at least one PN junction device, opposite a 1 st surface of the at least one PN junction device facing a front side of the semiconductor device where the at least one field-effect transistor is provided, and

wherein the back side contact plug is connected to one of a p-region and an n-region of the at least one PN junction device.

10 . The semiconductor device of claim 9 , further comprising a front side contact plug in the 1 st layer,

wherein the front side contact plug is on the 1 st surface of the at least one PN junction device, and

wherein the front side contact plug is connected to the other of the p-region and the n-region of the at least one PN junction device.

11 . The method of claim 6 , further comprising forming a back side contact plug in a via hole and on a surface of the at least one PN junction device.

12 . The method of claim 6 , further comprising forming a back side contact plug on a 2 nd surface of the at least one PN junction device, opposite a 1 st surface of the at least one PN junction device facing a front side of the semiconductor device where the at least one field-effect transistor is provided,

wherein the back side contact plug is connected to one of a p-region and an n-region of the at least one PN junction device.

13 . The method of claim 12 , further comprising forming a front side contact plug on the 1 st surface of the at least one PN junction device,

wherein the front side contact plug is connected to the other of the p-region and the n-region of the at least one PN junction device.