Embedded semiconductor region for a latch-up susceptibility improvement

1 . A structure, comprising:

a p-type region on a substrate and doped with a first doping concentration;

an n-type well on and horizontally surrounded completely by the p-type region, wherein the n-type well is doped with a second doping concentration;

a metal oxide semiconductor (MOS) device comprising first and second source/drain regions in the n-type well;

an embedded semiconductor region (ESR) on the p-type region and surrounding the n-type well, wherein a third doping concentration of the ESR is less than the first doping concentration of a portion of the p-type region in direct contact with the ESR, wherein a horizontal interface between the ESR and the p-type region is in contact with a vertical interface between the ESR and the p-type region, and wherein the horizontal interface extends under the n-type well; and

a p-type contact region on the p-type region and having a fourth doping concentration greater than the first doping concentration.

2 . The structure of claim 1 , further comprising an n-type region in the n-type well and adjacent to the MOS device, wherein a fifth doping concentration of the n-type region is greater than the second doping concentration.

3 . The structure of claim 1 , further comprising a p-type well on the p-type region, wherein the p-type contact region is in the p-type well.

4 . The structure of claim 1 , further comprising an intrinsic ESR surrounding the ESR.

5 . The structure of claim 1 , further comprising an other ESR surrounding the ESR, wherein the other ESR comprises p-type dopants, and wherein a fifth doping concentration of the other ESR is less the first doping concentration.

6 . The structure of claim 1 , wherein the ESR and the n-type well comprise same dopants.

7 . The structure of claim 1 , wherein the MOS device comprises first and second p-type source/drain (S/D) regions in the n-type well.

8 . A structure, comprising:

a first p-type region on a substrate;

a first n-type region on the first p-type region;

a metal oxide semiconductor (MOS) device on the first n-type region, wherein the MOS device comprises first and second source/drain regions in the first n-type region;

a second n-type region in the first n-type region, wherein doping concentrations of the first n-type region and the second n-type region are different;

a second p-type region on the first p-type region, wherein doping concentrations of the first p-type region and the second p-type region are different;

an embedded semiconductor region (ESR) surrounding the first n-type region, wherein a doping concentration of the ESR is lower than the doping concentrations of the first p-type region and the first n-type region, wherein a portion of the first p-type region is under the ESR, and wherein another portion of the first p-type region is between the ESR and the second p-type region; and

an intrinsic ESR surrounding the ESR and isolated from the ESR, wherein a horizontal interface between the intrinsic ESR and the first p-type region is coplanar with a horizontal interface between the ESR and the first p-type region.

9 . The structure of claim 8 , further comprising a third p-type region on the first p-type region and under the second p-type region, wherein a doping concentration of the third p-type region is different from the doping concentrations of the first and second p-type regions.

10 . The structure of claim 8 , wherein the ESR and the first n-type region comprise same dopants.

11 . The structure of claim 8 , wherein the MOS device is a PMOS device.

12 . The structure of claim 8 , wherein top surfaces of the second n-type region and the second p-type region are coplanar.

13 . A method, comprising:

forming an n-type well on a p-type region of a substrate;

doping a portion of the n-type well to form an n-type region in the n-type well;

forming a metal oxide semiconductor (MOS) device on the n-type well and isolated from the p-type region;

forming a p-type contact region in the p-type region;

forming an embedded semiconductor region (ESR) in direct contact with and surrounded by the p-type region, completely surrounding the n-type well along horizontal directions, and having a doping concentration less than those of the n-type well or the p-type region; and

forming another ESR surrounding and isolated from the ESR, wherein a first horizontal interface between the ESR and the p-type region is coplanar with a second horizontal interface between the other ESR and the p-type region.

14 . The method of claim 13 , wherein forming the ESR comprises forming n-type dopants in the ESR by ion implantation.

15 . The method of claim 13 , further comprising forming an intrinsic ESR surrounding the ESR and isolated from the ESR.

16 . The method of claim 13 , further comprising forming a p-type well below the p-type contact region and on the p-type region.

17 . The method of claim 13 , wherein forming the MOS device comprises forming a p-type source/drain region of the MOS device.

18 . The structure of claim 8 , wherein the MOS device is horizontally surrounded by the ESR along two orthogonal directions.

19 . The structure of claim 1 , further comprising another ESR surrounding the ESR, wherein bottom surfaces of the ESR and the other ESR are coplanar.

20 . The method of claim 13 , wherein forming the ESR comprises forming the first horizontal interface extending under the n-type well.