Display substrate having interlayer insulation layer with through hole formed therein, method for manufacturing the same and display panel
The present disclosure provides a display substrate, a method for manufacturing the display substrate and a display panel. The display substrate includes: a first semiconductor layer on a base substrate, where an active layer of the first thin film transistor is in the first semiconductor layer, and the active layer of the first thin film transistor at least comprises a channel region and a drain contact region; an interlayer insulation layer on a side of the first semiconductor layer away from the base substrate; and a first conductive layer on a side of the interlayer insulation layer away from the first semiconductor layer, wherein the pixel electrode is located in the first conductive layer, and the pixel electrode in the pixel unit is directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through a through hole.
1 . A display substrate, having a display region, wherein the display substrate comprises:
a base substrate;
a plurality of pixel units in the display region on the base substrate, wherein each of the plurality pixel units comprises a first thin film transistor and a pixel electrode;
an active layer of the first thin film transistor in a first semiconductor layer on the base substrate, and at least comprising a channel region and a drain contact region;
an interlayer insulation layer on a side of the first semiconductor layer away from the base substrate, wherein the interlayer insulation layer comprises a first insulation layer and a second insulation layer disposed in sequence on a side of the first semiconductor layer away from the base substrate;
a data line in the first insulation layer and on a side of the first semiconductor layer away from the base substrate;
a first through hole penetrating through the second insulation layer and a second through hole penetrating through the first insulation layer;
a first conductive layer on a side of the second insulation layer away from the first insulation layer, wherein the pixel electrode is located in the first conductive layer, and the pixel electrode in the pixel unit is directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through the first through hole and the second through hole, wherein
the data line comprises a plurality of data line segments sequentially connected together, each of the plurality of data line segments comprises a first signal line sub-segment extending along a first direction, a second signal line sub-segment extending along a second direction and a third signal line sub-segment extending along a third direction, with the first direction, the second direction, and the third direction being different from each other, the third signal line sub-segment, the first signal line sub-segment and the second signal line sub-segment being sequentially connected,
the active layer of the first thin film transistor comprises a first semiconductor structure extending along the first direction, a second semiconductor structure extending along a fifth direction, and a third semiconductor structure extending along the third direction, with the first direction, the fifth direction, and the third direction being different from each other and the third semiconductor structure, the first semiconductor structure and the second semiconductor structure being sequentially connected,
an orthographic projection of the third signal line sub-segment of the data line on the base substrate overlaps an entirety of an orthographic projection of the third semiconductor structure of the active layer on the base substrate, an orthographic projection of the first signal line sub-segment of the data line on the base substrate overlaps an entirety of an orthographic projection of the first semiconductor structure of the active layer on the base substrate, and an orthographic projection of the second signal line sub-segment of the data line on the base substrate overlaps a portion of an orthographic projection of the second semiconductor structure of the active layer on the base substrate, and
an orthographic projection of the first through hole on the base substrate overlaps with an orthographic projection of the second semiconductor structure on the base substrate.
2 . The display substrate of claim 1 , wherein an orthographic projection of the first through hole on the base substrate overlaps an orthographic projection of the second through hole on the base substrate.
3 . The display substrate of claim 2 , further comprising a third insulation layer comprising a filling structure and a support structure, wherein
the filling structure is in the first through hole; and
the support structure is on a side of the second insulation layer away from the base substrate.
4 . The display substrate of claim 3 , further comprising a second conductive layer and a third conductive layer, wherein
the first insulation layer comprises a first insulation sub-layer, a second insulation sub-layer, and a third insulation sub-layer,
the first insulation sub-layer is on a side of the first semiconductor layer away from the base substrate,
the second conductive layer is on a side of the first insulation sub-layer away from the base substrate and comprises a gate line and a gate electrode of the first thin film transistor,
the second insulation sub-layer is on a side of the second conductive layer away from the base substrate,
the third conductive layer is on a side of the second insulation sub-layer away from the base substrate and comprises the data line and a source electrode of the first thin film transistor, and
the third insulation sub-layer is on a side of the third conductive layer away from the base substrate.
5 . The display substrate of claim 4 , wherein
the second signal line sub-segment and the third signal line sub-segment are connected to each other to form a first included angle therebetween, and
the second signal line sub-segment and the third signal line sub-segment are located between two adjacent gate lines.
6 . The display substrate of claim 5 , wherein the first included angle is greater than or equal to 90° and less than 180°.
7 . The display substrate of claim 3 , wherein
the pixel electrode comprises a first pixel sub-electrode and a second pixel sub-electrode electrically connected to the first pixel sub-electrode,
the first pixel sub-electrode comprises a first portion and a second portion, wherein the first portion is in the first through hole and covers a sidewall and a bottom of the first through hole, and the second portion is filled in the second through hole and is connected to the drain contact region of the first thin film transistor,
the second pixel sub-electrode is on a side of the second insulation layer away from the base substrate and is connected to the first portion of the first pixel sub-electrode.
8 . The display substrate of claim 1 , wherein the first semiconductor structure and the second semiconductor structure form a second angle therebetween, with the second angle being greater than or equal to 90° and less than 180°.
9 . The display substrate of claim 1 , further comprising a fourth insulation layer, a fifth insulation layer, and a fourth conductive layer disposed between the first semiconductor layer and the base substrate; wherein
the fifth insulation layer is on a side of the first semiconductor layer proximal to the base substrate,
the fourth conductive layer is on a side of the fifth insulation layer proximal to the base substrate, the fourth conductive layer comprises a light shielding layer, and an orthographic projection of the light shielding layer on the base substrate covers an orthographic projection of the channel region of the first semiconductor layer on the base substrate, and
the fourth insulation layer is on a side of the fourth conductive layer proximal to the base substrate.
10 . The display substrate of claim 9 , wherein the display substrate further has a non-display region, and further comprises a gate driving circuit in the non-display region on the base substrate, and
the gate driving circuit comprises a second thin film transistor, and a gate electrode of the second thin film transistor is in the fourth conductive layer.
11 . The display substrate of claim 1 , further comprising:
a sixth insulation layer on a side of the first conductive layer away from the base substrate, and
a common electrode on a side of the sixth insulation layer away from the base substrate, wherein
an orthographic projection of the common electrode on the base substrate overlaps an orthographic projection of the pixel electrode on the base substrate.
12 . The display substrate of claim 1 , wherein a material of the active layer of the first thin film transistor comprises an oxide semiconductor.
13 . A display panel, comprising the display substrate of claim 1 .
14 . A method for manufacturing a display substrate, comprising:
providing a base substrate;
forming a plurality of pixel units in the display region on the base substrate, each of the plurality pixel units comprising a first thin film transistor and a pixel electrode;
forming an active layer of the first thin film transistor in a first semiconductor layer on the base substrate, with the active layer of the first thin film transistor at least comprising a channel region and a drain contact region;
forming a first insulation layer on the first semiconductor layer away from the base substrate;
forming a data line in the first insulation layer and on a side of the first semiconductor layer away from the base substrate;
forming a second through hole penetrating through the first insulation layer;
forming a second insulation layer on a side of the first insulation layer away from the base substrate;
forming a first through hole penetrating through the second insulation layer;
forming a first conductive layer on a side of the second insulation layer away from the first insulation layer, wherein the first conductive layer comprises the pixel electrode directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through the first and second through holes, wherein
forming the data line comprises: forming a plurality of data line segments sequentially connected together, such that each of the plurality of data line segments comprises a first signal line sub-segment extending along a first direction, a second signal line sub-segment extending along a second direction, and a third signal line sub-segment extending along a third direction, with the first direction, the second direction, and the third direction being different from each other, and the third signal line sub-segment, the first signal line sub-segment and the second signal line sub-segment being sequentially connected,
forming the active layer of the first thin film transistor in the first semiconductor layer, comprises: forming a first semiconductor structure of the active layer extending along the first direction, a second semiconductor structure of the active layer extending along a fifth direction, and a third semiconductor structure of the active layer extending along the third direction, with the first direction, the fifth direction, and the third direction being different from each other, and the third semiconductor structure, the first semiconductor structure and the second semiconductor structure being sequentially connected,
an orthographic projection of the third signal line sub-segment of the data line on the base substrate overlaps an entirety of an orthographic projection of the third semiconductor structure of the active layer on the base substrate, an orthographic projection of the first signal line sub-segment of the data line on the base substrate overlaps an entirety of an orthographic projection of the first semiconductor structure of the active layer on the base substrate, and an orthographic projection of the second signal line sub-segment of the data line on the base substrate overlaps a portion of an orthographic projection of the second semiconductor structure of the active layer on the base substrate, and
an orthographic projection of the first through hole on the base substrate overlaps with an orthographic projection of the second semiconductor structure on the base substrate.