Method of allocating widths for target signal lines, wiring substrate, light-emitting substrate and display device
A method of allocating widths for target signal lines, a wiring substrate, a light-emitting substrate and a display device are provided. The method includes numbering the target signal lines; performing the following operations at least once until the number of target signal lines in a set is zero, determining the set of target signal lines; determining a region R based on the conditions satisfied by a voltage drop V, a temperature rise T, and widths W of the target signal lines, determining the number i of the target signal line with the maximum voltage drop in the set; substituting a known length L i of the target signal line numbered i into V (L, W) to obtain V (L i , W) and obtaining W i based on an intersection of V (L i , W) and a boundary of the region R, and removing the target signal line with the width W i from the set.
1 . A method of allocating widths for target signal lines, comprising:
numbering at least one target signal line respectively;
performing the following operations at least once until a number of target signal lines to be allocated widths in a set is zero:
determining the set of target signal lines to be allocated widths;
determining a planar region R based on conditions satisfied by a voltage drop V and a temperature rise T of each of the target signal lines to be allocated widths and widths W of the target signal lines to be allocated widths, the voltage drop V being a function V (L, W) of a length L and a width W, the length L referring to a length of a sub-portion along a first direction, the width W referring to a width of the sub-portion along a second direction intersecting with the first direction, the sub-portion being a portion of each target signal line in a fan-out region and extending along the first direction;
determining a number i of a target signal line with a maximum voltage drop among the target signal lines to be allocated widths in the set;
substituting a known length L i of the target signal line numbered i into V (L, W) to obtain V (L i , W), obtaining a W i based on an intersection of V (L i , W) and a boundary of the planar region R, the W i being the width of the sub-portion of the target signal line numbered i along the second direction, the sub-portion of the target signal line numbered i being the portion of the target signal line numbered i in the fan-out region and extending along the first direction; and
removing the target signal line that has been allocated width W i from the set.
2 . The method according to claim 1 , wherein a number of the target signal lines is N, N is a positive integer greater than or equal to 2, the N target signal lines have N widths, a width of the target signal line with the maximum voltage drop among the N target signal lines is a maximum among the N widths.
3 . The method according to claim 1 - or 2 , wherein the temperature rise T is a function T (L, W) of the length L and the width W, the determining a planar region R based on conditions satisfied by a voltage drop V and a temperature rise T of each of the target signal lines to be allocated widths and widths W of the target signal lines to be allocated widths, comprises:
determining the planar region R based on a set of inequalities consisting of the following inequalities: the voltage drop V (L, W) of each of the target signal lines to be allocated widths being less than a voltage drop threshold, the temperature rise T (L, W) of each of the target signal lines to be allocated widths being less than a temperature rise threshold, and a sum of the widths W of the target signal lines to be allocated widths being less than a dynamic width threshold.
4 . The method according to claim 3 , wherein the determining a number i of a target signal line with a maximum voltage drop among the target signal lines to be allocated widths in the set, comprises:
substituting W 0 into V (L, W) to obtain V (L, W 0 ), W 0 being associated with the dynamic width threshold;
substituting the known length of each of the target signal lines to be allocated widths in the set into V (L, W 0 ) respectively to obtain a set of different voltage drops;
selecting a maximum voltage drop from the set of different voltage drops; and
determining the number i of the target signal line with the maximum voltage drop according to the known length corresponding to the maximum voltage drop.
5 . The method according to claim 1 , wherein the voltage drop V (L, W) of each target signal line satisfies the following formula:
V (L, W)=E+F*L/W, where both E and F are constants.
6 . The method according to claim 5 , wherein
V
(
L
,
W
)
=
R
pixel
*
∑
j
=
1
j
=
k
I
j
+
R
(
L
,
W
)
*
I
k
,
wherein the target signal lines are also in a functional region, the functional region comprises a plurality of partitions arranged in an array, R pixel is a resistance of a section of each target signal line corresponding to a single partition, k is a number of rows of the partitions, I j =j*I 0 , I k =k*I 0 , I 0 is a current of the single partition.
7 . The method according to claim 6 , wherein R (L, W)=R s *L/W, R s is a sheet resistance of the target signal line, E=k*(k+1)/2*I 0 *R pixel , F=k*I 0 *R s .
8 . The method according to claim 3 , wherein the temperature rise T (L, W) of each target signal line satisfies the following formula:
T
(
L
,
W
)
=
[
(
1
/
(
L
*
W
*
X
)
Y
)
/
(
I
/
C
)
]
1
/
Q
,
where I is a current transmitted by each target signal line, X, Y, C, Q are constants.
9 . A wiring substrate comprising:
a base substrate comprising a fan-out region; and
at least one target signal line on the base substrate and at least in the fan-out region, a sub-portion of each of the at least one target signal line having a length L along a first direction and a width W along a second direction intersecting with the first direction, the sub-portion being a portion of each of the at least one target signal line in the fan-out region and extending along the first direction,
wherein the width W of each target signal line is determined according to the method of claim 1 .
10 . The wiring substrate according to claim 9 , wherein a number of the target signal lines is N, N is a positive integer greater than or equal to 2, the N target signal lines have N widths, a width of the target signal line with a maximum voltage drop among the N target signal lines is a maximum among the N widths.
11 . The wiring substrate according to claim 9 , further comprising bonding electrodes in the fan-out region, wherein each target signal line is electrically connected to at least two bonding electrodes.
12 . The wiring substrate according to claim 9 , wherein the target signal line comprises at least one of a driving voltage signal line, a common voltage signal line, or a power supply voltage signal line.
13 . A light-emitting substrate comprising:
the wiring substrate according to claim 9 , wherein the base substrate further comprises a functional region comprising a plurality of partitions arranged in an array;
a plurality of light-emitting elements in the plurality of partitions in the functional region; and
a circuit board in the fan-out region.
14 . The light-emitting substrate according to claim 13 , wherein the plurality of partitions are in multiple rows and columns, a number of the target signal lines is N, N is a positive integer greater than or equal to 2, the N target signal lines are also in the functional region along the second direction, and the N target signal lines are in a same column of partitions or in M adjacent columns of partitions, M is a positive integer greater than or equal to 2.
15 . The light-emitting substrate according to claim 14 , wherein the circuit board comprises a chip on film, and the N target signal lines are electrically connected to a same circuit board via bonding electrodes.
16 . The light-emitting substrate according to claim 13 , wherein each of the plurality of light-emitting elements comprises a Mini light-emitting diode.
17 . A display device comprising the wiring substrate according to claim 9 .
18 . A display device comprising the light-emitting substrate according to claim 13 .