Display apparatus and method of manufacturing the same

1 . A method of manufacturing a display apparatus, the method comprising:

forming, on a substrate, a pixel circuit including a first transistor and a second transistor and a connection line connecting the first transistor with the second transistor;

performing an array test on the pixel circuit; and

disconnecting the connection line by removing a portion of the connection line between the first transistor and the second transistor.

2 . The method of claim 1 , wherein the forming, on the substrate, a pixel circuit including a first transistor and a second transistor and a connection line connecting the first transistor with the second transistor comprises:

forming, on the substrate, a first semiconductor layer and a second semiconductor layer;

forming a first insulating layer on the first semiconductor layer and the second semiconductor layer;

forming the connection line on the first insulating layer;

forming a second insulating layer on the connection line, wherein a first hole exposing at least a portion of the connection line is defined in the second insulating layer;

forming a first line and a second line on the second insulating layer;

forming a first organic insulating layer on the first line and the second line, wherein a second hole exposing at least a portion of the connection line is defined in the first organic insulating layer; and

forming a third line on the first organic insulating layer.

3 . The method of claim 2 , wherein the first transistor further includes a first gate electrode insulated from the first semiconductor layer, and

the first gate electrode and the connection line are formed on a same layer and include a same material.

4 . The method of claim 2 , wherein the first semiconductor layer and the connection line are connected to each other through the first line.

5 . The method of claim 2 , wherein the second semiconductor layer and the connection line are connected to each other through the second line.

6 . The method of claim 2 , further comprising: after the forming of the third line,

forming a second organic insulating layer on the third line, wherein a third hole for exposing at least a portion of the connection line is defined in the second organic insulating layer; and

forming a pattern material on the connection line and the second organic insulating layer.

7 . The method of claim 6 , wherein a width across the first hole is greater than a width across the second hole.

8 . The method of claim 6 , wherein a width across the second hole is greater than a width across the third hole.

9 . The method of claim 6 , wherein, in the disconnecting of the connection line, the pattern material is etched to form a pixel electrode, and the connection line is etched to form a disconnection portion.

10 . The method of claim 9 , wherein the pixel electrode does not overlap the disconnection portion.

11 . The method of claim 9 , further comprising, after the disconnecting of the connection line, forming a pixel defining layer for exposing at least a portion of the pixel electrode.

12 . The method of claim 11 , wherein at least a portion of the pixel defining layer is formed on the disconnection portion.

13 . The method of claim 12 , wherein the pixel defining layer directly contacts the connection line.

14 . The method of claim 1 , wherein the pixel circuit includes a first capacitor and a second capacitor.

15 . The method of claim 14 , wherein the first capacitor includes a first lower electrode and a first upper electrode insulated from the first lower electrode, and

the second capacitor includes a second lower electrode spaced apart from the first lower electrode and a second upper electrode insulated from the second lower electrode.