Display and electronic device

1 . A display, comprising:

a plurality of sub pixels;

a substrate;

a light-emitting device disposed on the substrate and located in a sub pixel;

a pixel circuit disposed on the substrate and located in the sub pixel, wherein the pixel circuit and the light-emitting device are coupled, wherein the pixel circuit comprises a first transistor and a second transistor, wherein an active layer of the first transistor comprises polycrystalline silicon, and wherein an active layer of the second transistor comprises semiconductor oxide;

an isolation portion disposed on the substrate and located in the sub pixel, wherein the isolation portion comprises an isolation base and an isolation retaining wall surrounding the isolation base, wherein the active layer of the second transistor is disposed in a groove formed by the isolation retaining wall and the isolation base, and wherein the isolation portion is configured to block hydrogen ions in the active layer of the first transistor from being diffused into the active layer of the second transistor; and

a common electrode layer located on a side that is of the first transistor and the second transistor, wherein a first pole of the first transistor or the second transistor is coupled to the common electrode layer, and wherein the isolation base and the common electrode layer are at a same layer, made of a same material, and integrally formed.

2 . The display according to claim 1 , wherein the display further comprises a first gate insulation layer, a first passivation layer, a second passivation layer, and a second gate insulation layer that are successively located on the substrate, wherein materials constituting the first passivation layer comprise silicon nitride, and wherein materials constituting the second passivation layer comprise silicon oxide;

wherein the first gate insulation layer is located between the active layer of the first transistor and a first gate, and wherein the first gate is covered by the first passivation layer and the second passivation layer; and

wherein the isolation retaining wall penetrates at least the first gate insulation layer and the first passivation layer, wherein at least a portion of the second gate insulation layer is located in the isolation retaining wall, and wherein the second gate insulation layer is located between the active layer of the second transistor and a second gate.

3 . The display according to claim 2 , wherein the isolation retaining wall further penetrates the second passivation layer.

4 . The display according to claim 1 , wherein the common electrode layer comprises a metal layer;

wherein a vertical projection of the active layer of the first transistor on the substrate is located within a range of a vertical projection of the common electrode layer on the substrate; and

wherein a vertical projection of the active layer of the second transistor on the substrate is located within the range of the vertical projection of the common electrode layer on the substrate.

5 . The display according to claim 1 , wherein the first transistor further comprises a third gate located on a side that is of a first gate of the first transistor, wherein the first gate of the first transistor is insulated from the third gate; and

wherein the third gate of the first transistor is at a same layer and made of a same material as the common electrode layer, and is insulated from the common electrode layer.

6 . The display according to claim 1 , wherein the second transistor further comprises a fourth gate located on a side that is of a second gate of the second transistor, and the second gate of the second transistor is insulated from the fourth gate; and

wherein the fourth gate of the second transistor is at a same layer and made of a same material as the common electrode layer, and is insulated from the common electrode layer.

7 . The display according to claim 1 , wherein materials constituting the substrate comprise an organic material;

wherein the display further comprises a first barrier layer, a first stress relief layer, and a second barrier layer that are sequentially located on the substrate, wherein the active layer of the first transistor is located on a surface of a side that is of the second barrier layer and that is away from the substrate; and

wherein the common electrode layer is located between the first barrier layer and the first stress relief layer, and is connected to the first barrier layer and the first stress relief layer.

8 . The display according to claim 7 , wherein the display further comprises a first via, wherein the first via sequentially penetrates through the first stress relief layer, the second barrier layer, a first gate insulation layer, and a first passivation layer, wherein a first end of the first via is coupled to the common electrode layer, and wherein a second end of the first via is coupled to the first pole of the first transistor or the second transistor; and

wherein the first via comprises a first metal conductive layer, wherein the isolation retaining wall and the first metal conductive layer are at a same layer and made of a same material.

9 . The display according to claim 8 , wherein the display further comprises a second via, wherein a first end of the second via is coupled to the second end of the first via, and wherein a second end of the second via is coupled to the first pole of the first transistor or the second transistor; and

wherein the second via comprises a second metal conductive layer, wherein the second metal conductive layer and the first pole of the first transistor or the second transistor are at a same layer and made of a same material.

10 . The display according to claim 1 , wherein materials constituting the substrate comprise an organic material;

wherein the display further comprises a first barrier layer, a connection layer, and a first stress relief layer that are sequentially located on the substrate, wherein the connection layer is configured to connect the first barrier layer to the first stress relief layer; and

wherein:

the common electrode layer is located between the substrate and the first barrier layer, and is connected to the substrate and the first barrier layer; or

the display further comprises a second barrier layer located on a side that is of the first stress relief layer and that is away from the substrate, the active layer of the first transistor is located on a surface of a side that is of the second barrier layer and that is away from the substrate, and the common electrode layer is located between the first stress relief layer and the second barrier layer, and is connected to the first stress relief layer and the second barrier layer.

11 . The display according to claim 7 , wherein the active layer of the second transistor is insulated from the isolation base, and wherein the second barrier layer is disposed on an outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor.

12 . The display according to claim 1 , wherein materials constituting the substrate comprise an inorganic material;

wherein the display further comprises a buffer layer located on the substrate, wherein the common electrode layer is located between the substrate and the buffer layer, and is connected to the substrate and the buffer layer; and

wherein the active layer of the second transistor is insulated from the isolation base, and the buffer layer is disposed on an outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor.

13 . The display according to claim 2 , wherein the pixel circuit further comprises a storage capacitor comprising a first electrode and a second electrode that are insulated;

wherein the first electrode is located on a surface of a side that is of the first gate insulation layer and that is away from the substrate, and the first electrode and a gate of the first transistor are at a same layer and made of a same material; and

wherein the second electrode is located on a surface of a side that is of the second passivation layer and that is away from the substrate, the second electrode is coupled to the first transistor, and the second electrode and a gate of the second transistor are at a same layer and made of a same material.

14 . The display according to claim 13 , wherein the display further comprises a third passivation layer that covers the second gate insulation layer;

wherein the storage capacitor further comprises a third electrode located on a surface of a side that is of the third passivation layer, that is away from the substrate, and that covers the second electrode, wherein the third electrode and the first pole of the first transistor or the second transistor are at a same layer and made of a same material; and

wherein the display further comprises a third via that penetrates the second electrode, wherein the third electrode is coupled to the first electrode through the third via.

15 . The display according to claim 1 , wherein the first transistor is coupled to the light-emitting device, and the first transistor is configured to provide a driving current to the light-emitting device.

16 . An electronic device, comprising:

a display, wherein the display comprises:

a plurality of sub pixels;

a substrate;

a light-emitting device disposed on the substrate and located in a sub pixel;

a pixel circuit disposed on the substrate and located in the sub pixel, wherein the pixel circuit and the light-emitting device are coupled, wherein the pixel circuit comprises a first transistor and a second transistor, wherein an active layer of the first transistor comprises polycrystalline silicon, and wherein an active layer of the second transistor comprises semiconductor oxide;

an isolation portion disposed on the substrate and located in the sub pixel, wherein the isolation portion comprises an isolation base and an isolation retaining wall surrounding the isolation base, wherein the active layer of the second transistor is disposed in a groove formed by the isolation retaining wall and the isolation base, and wherein the isolation portion is configured to block hydrogen ions in the active layer of the first transistor from being diffused into the active layer of the second transistor; and

a common electrode layer located on a side that is of the first transistor and the second transistor, wherein a first pole of the first transistor or the second transistor is coupled to the common electrode layer, and wherein the isolation base and the common electrode layer are at a same layer, made of a same material, and integrally formed.

17 . A display, comprising:

a plurality of sub pixels;

a substrate;

a light-emitting device disposed on the substrate and located in a sub pixel;

a pixel circuit disposed on the substrate and located in the sub pixel, wherein the pixel circuit and the light-emitting device are coupled, wherein the pixel circuit comprises a first transistor and a second transistor, wherein an active layer of the first transistor comprises polycrystalline silicon, and wherein an active layer of the second transistor comprises semiconductor oxide; and

an isolation portion disposed on the substrate and located in the sub pixel, wherein the isolation portion comprises an isolation base and an isolation retaining wall surrounding the isolation base, wherein the active layer of the second transistor is disposed in a groove formed by the isolation retaining wall and the isolation base, and wherein the isolation portion is configured to block hydrogen ions in the active layer of the first transistor from being diffused into the active layer of the second transistor;

wherein the display further comprises a first gate insulation layer, a first passivation layer, a second passivation layer, and a second gate insulation layer that are successively located on the substrate, wherein materials constituting the first passivation layer comprise silicon nitride, and wherein materials constituting the second passivation layer comprise silicon oxide;

wherein the first gate insulation layer is located between the active layer of the first transistor and a first gate, and wherein the first gate is covered by the first passivation layer and the second passivation layer;

wherein the isolation retaining wall penetrates at least the first gate insulation layer and the first passivation layer, wherein at least a portion of the second gate insulation layer is located in the isolation retaining wall, and wherein the second gate insulation layer is located between the active layer of the second transistor and a second gate;

wherein the pixel circuit further comprises a storage capacitor comprising a first electrode and a second electrode that are insulated;

wherein the first electrode is located on a surface of a side that is of the first gate insulation layer and that is away from the substrate, and the first electrode and a gate of the first transistor are at a same layer and made of a same material; and

wherein the second electrode is located on a surface of a side that is of the second passivation layer and that is away from the substrate, the second electrode is coupled to the first transistor, and the second electrode and a gate of the second transistor are at a same layer and made of a same material.

18 . The display according to claim 17 , wherein the isolation retaining wall further penetrates the second passivation layer.

19 . The display according to claim 17 , wherein the display further comprises a third passivation layer that covers the second gate insulation layer;

wherein the storage capacitor further comprises a third electrode located on a surface of a side that is of the third passivation layer, that is away from the substrate, and that covers the second electrode, wherein the third electrode and the first pole of the first transistor or the second transistor are at a same layer and made of a same material; and

wherein the display further comprises a third via that penetrates the second electrode, wherein the third electrode is coupled to the first electrode through the third via.

20 . The display according to claim 17 , wherein the first transistor is coupled to the light-emitting device, and the first transistor is configured to provide a driving current to the light-emitting device.