Phase change heterostructure, and phase change memory device including the same
Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.
1 . A phase change heterostructure comprising:
a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other,
wherein a thermal conductivity of a material of the plurality of thermal barrier layers is lower than a thermal conductivity of a material of the plurality of phase change material layers, and
wherein the plurality of phase change material layers and the plurality of thermal barrier layers are alternately stacked directly on each other so a corresponding one of the plurality of phase change material layers is directly connected to an overlying one of the plurality of thermal barrier layers and an underlying one of the plurality of thermal barrier layers.
2 . The phase change heterostructure of claim 1 , wherein
the plurality of thermal barrier layers comprise a chalcogenide material having a composition of AB 2 , wherein
A is a metal element, and
B is a chalcogen element.
3 . The phase change heterostructure of claim 2 , wherein
in the composition AB 2 , A comprises at least one of Ti, Zr, Hf, Ta, Mo, and W, and
in the composition AB 2 , B comprises at least one of Te, Se, and S.
4 . The phase change heterostructure of claim 1 , wherein
the thermal conductivity of the material of the plurality of thermal barrier layers is 2% to 10% of the thermal conductivity of the material of the plurality of phase change material layers.
5 . The phase change heterostructure of claim 1 , wherein the plurality of thermal barrier layers comprise a material having a thermal conductivity of lower than 1 W/mK.
6 . The phase change heterostructure of claim 1 , wherein each of the plurality of thermal barrier layers has a thickness of 2 nm or more and 10 nm or less.
7 . The phase change heterostructure of claim 1 , wherein the plurality of phase change material layers comprise at least one of Sb 2 Te 3 and Ge 2 Sb 2 Te 5 .
8 . The phase change heterostructure of claim 7 , wherein the plurality of phase change material layers further include a carbon dopant.
9 . The phase change heterostructure of claim 1 , wherein each of the plurality of phase change material layers has a thickness of 2 nm or more and 10 nm or less.
10 . A phase change memory device comprising:
a plurality of memory cells,
each of the plurality of memory cells including a first electrode, a second electrode spaced apart from the first electrode, and a phase change heterostructure between the first electrode and the second electrode,
the phase change heterostructure including a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other,
wherein a thermal conductivity of a material of the plurality of thermal barrier layers is lower than a thermal conductivity of a material of the plurality of phase change material layers, and
wherein the plurality of phase change material layers and the plurality of thermal barrier layers are alternately stacked directly on each other so a corresponding one of the plurality of phase change material layers is directly connected to an overlying one of the plurality of thermal barrier layers and an underlying one of the plurality of thermal barrier layers.
11 . The phase change memory device of claim 10 , wherein the phase change memory device has a three-dimensional (3D) cross point array structure.
12 . The phase change memory device of claim 11 , wherein each of the plurality of memory cells further comprises a switching element connected in series with the phase change heterostructure.
13 . The phase change memory device of claim 10 , wherein the phase change memory device has a vertically stacked structure.
14 . The phase change memory device of claim 10 , wherein
the plurality of thermal barrier layers comprise a chalcogenide material having a composition of AB 2 ,
A is a metal element, and
B is a chalcogen element.
15 . The phase change memory device of claim 14 , wherein
in the composition AB 2 , A comprises at least one of Ti, Zr, Hf, Ta, Mo, and W, and
in the composition AB 2 , B comprises at least one of Te, Se, and S.
16 . The phase change memory device of claim 10 , wherein
the thermal conductivity of the material of the plurality of thermal barrier layers is 2% to 10% of the thermal conductivity of the material of the plurality of phase change material layers.
17 . The phase change memory device of claim 10 , wherein the thermal conductivity of the material of the plurality of thermal barrier layers comprise a material having a thermal conductivity of lower than 1 W/mK.
18 . The phase change memory device of claim 10 , wherein each of the plurality of thermal barrier layers has a thickness of 2 nm or more and 10 nm or less.