Transistor structure and methods of forming the same
Provided is an epitaxial design/structure and transistor platform for a III-N transistor/chip incorporating a backside conductive/metal layer. The backside metal may serve several functions in the transistor/chip, including serving as a back gate, a field plate, and an electrode to deliver power to the devices and circuits, for example, as part of a backside power delivery network (BSPDN). Also provided are methods of preparing/fabricating the epitaxial design/structure and transistor platform described herein.
1 . A method of forming an epitaxial structure comprising:
forming a buffer layer on a substrate;
forming a first etch stop layer on the buffer layer;
forming a first cap layer on the first etch stop layer;
forming a second etch stop layer on the first cap layer;
forming a first polarization charge-inducer/barrier layer on the second etch stop layer;
forming a channel on the first charge-inducer/barrier layer;
forming a second polarization charge-inducer/barrier layer on the channel; and
forming a second cap layer on the second polarization charge-inducer/barrier layer,
wherein the buffer layer, first etch stop layer, first cap layer, second etch stop layer, first polarization charge-inducer/barrier layer, channel, second polarization charge-inducer/barrier layer, and second cap layer are grown in the metal/top face on top of the substrate, and:
depositing and patterning a conductive layer on the second polarization charge-inducer/barrier layer;
forming a bonding dielectric on the patterned conductive layer,
to provide a structure wherein the bonding dielectric is at the top of the structure, followed by:
orienting the structure so that the bonding dielectric and the patterned conductive layer are at the bottom of the structure, and the substrate is at the top of the structure;
removing the substrate and buffer layer;
forming source and drain electrodes on opposing sides of the channel; and
forming a gate electrode/top gate on top of the channel,
wherein at least one layer in the epitaxial structure is grown epitaxially, to provide the epitaxial structure.
2 . The method of claim 1 , further comprising bonding a mechanical wafer to the bonding dielectric before or after orienting the epitaxial structure so that the bonding dielectric and the patterned conductive layer are at the bottom of the structure.
3 . The method of claim 1 , wherein all the layers in the epitaxial structure are grown epitaxially on the substrate.
4 . The method of claim 1 , wherein the first polarization charge-inducer/barrier layer and the channel comprise different III-N semiconductor materials.
5 . The method of claim 1 , wherein the second polarization charge-inducer/barrier layer and the channel comprise different III-N semiconductor materials, and wherein the III-N semiconductor material of the second polarization charge-inducer/barrier layer has a greater band gap than that of the III-N semiconductor material of the channel.
6 . The method of claim 1 , wherein the first etch stop layer comprises a material that has an etching rate less than the etching rate of the substrate.
7 . The method of claim 6 , wherein the first etch stop layer comprises Al a Ga 1-a N, wherein the mole fraction a of Al is 0<a≤1.
8 . The method of claim 1 , wherein the second etch stop layer comprises a material that has an etching rate less than the etching rate of the first cap layer.
9 . The method of claim 8 , wherein the first etch stop layer comprises Al b Ga 1-b N, wherein the mole fraction a of Al is 0<b≤1.
10 . The method of claim 1 , wherein the second cap layer comprises a III-N semiconductor material or silicon nitride.
11 . An epitaxial structure prepared by the method of claim 1 .
12 . A method of forming an epitaxial structure comprising:
a) forming a buffer layer on a substrate;
b) forming a channel on the buffer layer
c) forming a polarization charge-inducer/barrier layer on the channel; wherein the buffer layer, channel, and polarization charge-inducer/barrier layer are grown in the metal/top face on top of the substrate, followed by:
d) depositing and patterning a conductive layer on the polarization charge-inducer/barrier layer;
e) forming a bonding dielectric on the patterned conductive,
to provide a structure wherein the bonding dielectric is at the top of the structure, followed by:
f) orienting the epitaxial structure so that the bonding dielectric and the patterned conductive layer are at the bottom of the structure, and the substrate is at the top of the structure;
g) removing the substrate and buffer layer;
h) forming source and drain electrodes on opposing sides of the channel;
i) forming a gate electrode/top gate on top of the channel, wherein at least one layer in the epitaxial structure is grown epitaxially, to provide the epitaxial structure; and
bonding a mechanical wafer to the bonding dielectric before or after orienting the epitaxial structure so that the bonding dielectric and the patterned conductive layer are at the bottom of the structure.
13 . The method of claim 12 , wherein all the layers in the epitaxial structure are grown epitaxially on the substrate.