Low resistance interconnect features and method for manufacturing the same

1 . A method for manufacturing a semiconductor structure, comprising:

forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature;

forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material, the first cap element having a first surface facing the first conductive element, and a second surface opposite to the first surface;

forming a second dielectric feature with a first opening that exposes the first cap element;

forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer;

after forming the barrier layer, removing a portion of the first cap element exposed from the barrier layer so that the first cap element has a through hole extending from the second surface to the first surface; and

forming a second conductive element in the first opening and the through hole,

wherein the first cap feature further includes a metallic element which is formed over the first conductive element prior to forming the first cap element, and

wherein after removing the portion of the first cap element, the metallic element remains to prevent exposure of the first conductive element through the through hole.

2 . The method according to claim 1 , wherein the two-dimensional material includes graphene.

3 . The method according to claim 1 , further comprising:

forming a third dielectric feature with a second opening in position corresponding to the second conductive element;

forming another barrier layer over the third dielectric feature; and

forming a third conductive element in the second opening so that the third conductive element is electrically connected to the second conductive element.

4 . The method according to claim 3 , further comprising:

prior to forming the third dielectric feature, forming a second cap feature over the second conductive element, the second cap feature including a second cap element which includes graphene such that after forming the third dielectric feature, the second cap element is exposed from the third dielectric feature, and such that after forming the another barrier layer, the second cap element is exposed from the another barrier layer; and

prior to forming the third conductive element, removing a portion of the second cap element exposed from the another barrier layer.

5 . The method according to claim 1 , wherein the second conductive element is connected to the first conductive element through the metallic element.

6 . A method for manufacturing a semiconductor structure, comprising:

forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature;

forming a blocking layer over the first conductive element;

forming a second dielectric feature with an opening that exposes a portion of the blocking layer;

performing a selective deposition process to form a barrier layer in a manner that a material of the barrier layer is selectively deposited on the second dielectric feature without being deposited on the portion of the blocking layer;

after the selective deposition process, removing the portion of the blocking layer; and

forming a second conductive element in the opening.

7 . The method according to claim 6 , after forming the barrier layer and prior to forming the second conductive element in the opening, further comprising forming a liner layer over the barrier layer.

8 . The method according to claim 7 , wherein formation of the liner layer is performed after removing the portion of the blocking layer.

9 . The method according to claim 7 , wherein formation of the liner layer is performed before removing the portion of the blocking layer, and formation of the liner layer on the portion of blocking layer is inhibited.

10 . The method according to claim 7 , wherein formation of the liner layer is performed after removing the portion of the blocking layer, the method further comprising, after removing the portion of the blocking layer and prior to forming the second conductive element in the opening,

forming an additional blocking layer in position at which the portion of the blocking layer is removed, the additional blocking layer being made of a material different from that of the blocking layer;

forming a liner layer over the barrier layer while formation of the liner layer on the additional blocking layer is inhibited; and

removing the additional blocking layer.

11 . The method according to claim 10 , wherein

after removing the portion of the blocking layer, a portion of the first conductive element is exposed; and

the blocking layer is made of graphene, and the additional blocking layer is made of a material that selectively deposits on the first conductive element and that inhibits formation of the liner layer on the additional blocking layer.

12 . The method according to claim 10 , further comprising forming a metallic element between the blocking layer and the first conductive element such that after removing the portion of the blocking layer, a portion of the metallic element is exposed, wherein the blocking layer is made of graphene, and the additional blocking layer is made of a material that selectively deposits on the metallic element and that inhibits formation of the liner layer on the additional blocking layer.

13 . A method for manufacturing a semiconductor structure, comprising:

forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature;

forming a first cap feature including a first cap element disposed on the first conductive element, the first cap element including a two-dimensional material;

forming a second dielectric feature over the first dielectric feature, the first cap feature and the first interconnect feature, the second dielectric feature having an upper surface distal from the first dielectric feature, and a lower surface opposite to the upper surface, the second dielectric feature including a three-dimensional material; and

forming a second interconnect feature including

forming a conductive portion extending through the second dielectric feature and the first cap element,

prior to forming the conductive portion, forming a barrier layer extending from the upper surface to terminate at the lower surface of the second dielectric feature such that the conductive portion is separated from the second dielectric feature through the barrier layer, the barrier layer being formed by a selective deposition process in a manner that the barrier layer is selectively deposited on the three-dimensional material without being deposited on the two-dimensional material such that the barrier layer is absent between the first conductive element and the conductive portion, and

after forming the barrier layer and prior to forming the conductive portion, removing a portion of the first cap element exposed from the barrier layer such that the conductive portion is formed to extend through the first cap element.

14 . The method according to claim 13 , wherein the two-dimensional material includes graphene.

15 . The method according to claim 13 , wherein the first cap feature further includes a metallic element which is disposed between the first cap element and the first conductive element, the conductive portion being connected to the first conductive element through the metallic element.

16 . The method according to claim 15 , wherein the metallic element includes one of copper, cobalt, ruthenium, aluminum copper, cobalt tungsten, ruthenium cobalt, and combinations thereof.

17 . The method according to claim 13 , wherein forming the conductive portion includes depositing a second conductive element, and prior to depositing the second conductive element, depositing a liner layer so that after depositing the second conductive element, the liner layer is disposed between the second conductive element and the barrier layer.

18 . The method according to claim 17 , wherein the liner layer has an end region which extends through the first cap element and which is disposed around an end region of the second conductive element.

19 . The method according to claim 17 , wherein the second conductive element extends through the first cap element, and the liner layer is absent between the first conductive element and the second conductive element.

20 . The method according to claim 19 , wherein the second conductive element has a main region formed in the second dielectric feature, and an end region formed in the first cap element, a maximum dimension of the end region being larger than a minimum dimension of the main region.