Self-aligned contact based via to backside power rail
According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is adjacent to and parallel to the first nanodevice along an x-axis. A dielectric fill is located between the first nanodevice and the second nanodevice. A dielectric liner is comprised of a first dielectric liner and a second dielectric liner. The first dielectric liner is located between the first nanodevice and the dielectric fill. The second dielectric liner is located between the second nanodevice and the dielectric fill. A plurality of self-aligned contact (SAC) caps is comprised of a head section and a shaft section. The head section extends a first width parallel to the x-axis and is in direct contact with a frontside of the dielectric liner. The shaft section extends a second width parallel to the x-axis. The first width is greater than the second width.
1 . A semiconductor device comprising:
a first nanodevice comprised of a plurality of first transistors;
a second nanodevice comprised of a plurality of second transistors, wherein the second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis;
a dielectric fill located between the first nanodevice and the second nanodevice;
a dielectric liner comprised of a first dielectric liner and a second dielectric liner, wherein the first dielectric liner is located between the first nanodevice and the dielectric fill, and wherein the second dielectric liner is located between the second nanodevice and the dielectric fill; and
a plurality of self-aligned contact (SAC) caps comprised of a head section and a shaft section, wherein the head section of each SAC cap extends a first width parallel to the x-axis and is in direct contact with a frontside of the dielectric liner, wherein the shaft section extends a second width parallel to the x-axis, wherein the first width is greater than the second width, and wherein the head section and the shaft section of the plurality of SAC caps have a T-shape.
2 . The semiconductor device of claim 1 , wherein each of the first dielectric liner and the second dielectric liner is defined by a recess.
3 . The semiconductor device of claim 2 , wherein the head section of each SAC cap extends downwards through the recess to connect to the frontside of the dielectric liner.
4 . The semiconductor device of claim 1 , wherein at least a portion of the head section of each SAC cap is in direct contact with the dielectric fill.
5 . A semiconductor device comprising:
a first nanodevice comprised of a plurality of first transistors;
a second nanodevice comprised of a plurality of second transistors, wherein the second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis;
a dielectric fill located between the first nanodevice and the second nanodevice;
a dielectric liner comprised of a first dielectric liner and a second dielectric liner, wherein the first dielectric liner is located between the first nanodevice and the dielectric fill, and wherein the second dielectric liner is located between the second nanodevice and the dielectric fill;
a plurality of self-aligned contact (SAC) caps comprised of a head section and a shaft section, wherein the head section of each SAC cap extends a first width parallel to the x-axis and is in direct contact with a frontside of the dielectric liner, wherein the shaft section extends a second width parallel to the x-axis, and wherein the first width is greater than the second width; and
a plurality of gate spacers in direct contact with the head section and the shaft section of each SAC cap.
6 . The semiconductor device of claim 5 , wherein each gate spacer is defined by a recess.
7 . The semiconductor device of claim 6 , wherein the head section of each SAC cap extends parallel to the x-axis through the recess to connect to the frontside of the dielectric liner.
8 . The semiconductor device of claim 5 , wherein the head section and the shaft section of the plurality of SAC caps have a T-shape.
9 . The semiconductor device of claim 8 , wherein each gate spacer is located in a seat of the T.
10 . A semiconductor device comprising:
a first nanodevice comprised of a plurality of first transistors, wherein the first nanodevice includes a first source/drain contact and a second source/drain contact;
a second nanodevice comprised of a plurality of second transistors, wherein the second nanodevice includes a third source/drain contact and a fourth source/drain contact, and wherein the second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis;
a dielectric fill located between the first nanodevice and the second nanodevice;
a dielectric liner comprised of a first dielectric liner and a second dielectric liner, wherein the first dielectric liner is located between the first nanodevice and the dielectric fill, and wherein the second dielectric liner is located between the second nanodevice and the dielectric fill;
a plurality of self-aligned contact (SAC) caps comprised of a head section and a shaft section, wherein the head section of each SAC cap extends a first width parallel to the x-axis and is in direct contact with a frontside of the dielectric liner, wherein the shaft section extends a second width parallel to the x-axis, and wherein the first width is greater than the second width; and
a plurality of gate spacers in direct contact with the head section and the shaft section of each SAC cap.
11 . The semiconductor device of claim 10 , further comprising:
a power via (VBPR) located between the first dielectric liner and the second dielectric liner.
12 . The semiconductor device of claim 11 , further comprising:
a source/drain contact-VBPR link located between the VBPR and the second source/drain contact.
13 . The semiconductor device of claim 12 , wherein the source/drain contact-VBPR link connects the second source/drain contact to the VBPR.
14 . The semiconductor device of claim 13 , wherein the first dielectric liner is defined by a recess.
15 . The semiconductor device of claim 14 , wherein the source/drain contact-VBPR link extends downwards through the recess to connect to a frontside of the first dielectric liner.
16 . The semiconductor device of claim 15 , wherein the source/drain contact-VBPR link and a head section of at least one SAC cap are substantially in a same plane.
17 . The semiconductor device of claim 16 , wherein the source/drain contact-VBPR link is in direct contact with the head section of the at least one SAC cap.
18 . The semiconductor device of claim 17 , wherein a height of the second dielectric liner is greater than a height of the first dielectric liner.
19 . The semiconductor device of claim 18 , wherein the head section of the at least one SAC cap extends downwards through the recess to connect to the frontside of the dielectric liner.