Semiconductor interconnection structures and methods of forming the same
An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.
1 . A method of forming an interconnection structure, comprising:
forming a dielectric layer over a substrate;
forming a sacrificial dielectric layer over the dielectric layer;
forming a plurality of first openings extending through the sacrificial dielectric layer;
extending at least one of the first openings further through the dielectric layer to form a second opening, thereby defining the dielectric layer as a second dielectric layer;
after forming the second opening, forming a conformal barrier and a blocking layer at a bottom of the second opening;
removing the blocking layer;
filling the first openings and the second opening with conductive material to simultaneously form a plurality of first conductive structures within the sacrificial dielectric layer and a second conductive structure extending through the sacrificial dielectric layer and the second dielectric layer, respectively;
removing the sacrificial dielectric layer remaining in gaps between the first and second conductive structures;
filling the gaps with a dielectric material conformally around the first conductive structures and the second conductive structure without subjecting the dielectric material to an etching process, thereby forming a first dielectric layer positioned above the second dielectric layer;
forming an etch stop layer to cover at least portions of the first conductive structure; and
forming a conductive layer over the etch stop layer.
2 . The method of claim 1 , further comprising filling the gaps with dielectric materials with a dielectric constant smaller than a predetermined value for the first dielectric layer.
3 . The method of claim 1 , further comprising filling the gaps partially or completely with air to form air gaps in the first dielectric layer.
4 . The method of claim 1 , further comprising:
forming a liner layer on sidewalls and bottoms of the first openings, on sidewalls of the second opening, and on the blocking layer before forming the conformal barrier, wherein the liner layer comprises silicon nitride, silicon carbon nitride, or silicon oxycarbonitride, and
wherein removing the blocking layer also removes portions of the liner layer and the conformal barrier disposed on the blocking layer, such that the second conductive structure directly contacts an underlying conductive layer.
5 . The method of claim 1 , further comprising:
after filling the gaps with the dielectric material, planarizing the dielectric material to expose top surfaces of the first conductive structures and the second conductive structure;
performing a pretreatment to clean the exposed top surfaces; and
selectively forming a capping layer on the exposed top surfaces of the first conductive structures and the second conductive structure, wherein the capping layer comprises cobalt.
6 . A method of forming an interconnection structure, comprising:
forming a plurality of metallization layers over a substrate, wherein forming at least one metallization layer of the plurality of metallization layers comprises:
forming a dielectric layer over an underlying metallization layer or the substrate;
forming a sacrificial dielectric layer over the dielectric layer;
forming a plurality of first openings extending through the sacrificial dielectric layer;
extending at least one of the first openings through the dielectric layer to form a second opening configured to interconnect with the underlying metallization layer, thereby defining the dielectric layer as a second dielectric layer;
filling the first openings and the second opening with a conductive material to simultaneously form a plurality of first conductive structures within the sacrificial dielectric layer and a second conductive structure extending vertically through the sacrificial dielectric layer and the second dielectric layer to the underlying metallization layer;
removing the sacrificial dielectric layer to form gaps between the first conductive structures and the second conductive structure; and
filling the gaps with an etching-process-free dielectric material conformally around the first conductive structures and the second conductive structure without subjecting the dielectric material to an etching process, thereby forming a first dielectric layer positioned above the second dielectric layer,
wherein the etching-process-free dielectric material forms the first dielectric layer comprising air gaps selectively formed in spaces between adjacent first conductive structures where a pitch is smaller than a predetermined value.
7 . The method of claim 6 , wherein filling the gaps with the etching-process-free dielectric material to form the first dielectric layer comprises depositing the dielectric material by plasma-enhanced chemical vapor deposition (PECVD) after removing the sacrificial dielectric layer.
8 . The method of claim 6 , further comprising:
forming a barrier layer on sidewalls and bottoms of the first openings and the second opening prior to filling with the conductive material.
9 . The method of claim 6 , wherein removing the sacrificial dielectric layer comprises performing a selective ashing process to decompose the sacrificial dielectric layer while protecting the first conductive structures and the second conductive structure with a photoresist mask.
10 . The method of claim 6 , wherein the second conductive structure comprises a conductive via electrically connecting the at least one metallization layer to the underlying metallization layer, and wherein the conductive material is electroplated into the first openings and the second opening.
11 . The method of claim 6 , wherein the etching-process-free dielectric material for the first dielectric layer has a dielectric constant lower than that of the second dielectric layer.
12 . The method of claim 6 , further comprising:
forming a second blocking layer on the dielectric material after planarizing;
selectively forming a second dielectric layer on the capping layer, wherein the second dielectric layer comprises a metal oxide or metal nitride;
removing the second blocking layer;
conformally forming an etch stop layer over the dielectric material, the second dielectric layer, and sidewalls of the first conductive structures and the second conductive structure; and
removing portions of the etch stop layer to expose portions of the second dielectric layer and the dielectric material.
13 . A method of forming an interconnection structure, comprising:
forming a lower conductive layer within a first dielectric layer over a substrate;
forming an inter-level dielectric layer over the first dielectric layer;
forming a conductive via through the inter-level dielectric layer to electrically connect the lower conductive layer and an upper conductive layer;
forming a sacrificial dielectric layer surrounding the conductive via and the upper conductive layer;
removing the sacrificial dielectric layer after forming the conductive via and upper conductive layer;
annealing the interconnection structure to seal exposed surfaces of the conductive via and the upper conductive feature; and
filling regions created as a result of removal of the sacrificial dielectric layer with an etching-process-free dielectric material.
14 . The method of claim 13 , wherein the etching-process-free dielectric material is deposited by a flowable-oxide, spin-on-dielectric, or atomic-layer-deposition process.
15 . The method of claim 13 , wherein the etching-process-free dielectric material comprises a porous SiCOH, BN, or BC material having a dielectric constant lower than 2.5.
16 . The method of claim 13 , wherein the etching-process-free dielectric material comprises a carbon-rich polymer removable by an oxygen-based plasma or solvent exposure process.
17 . The method of claim 13 , wherein the inter-level dielectric layer is formed by plasma-enhanced chemical-vapor deposition (PECVD).
18 . The method of claim 13 , wherein the conductive via and the upper conductive feature are simultaneously filled in a dual-damascene process prior to removal of the sacrificial dielectric layer.
19 . The method of claim 13 , wherein the etching-process-free dielectric material comprises an air-gap region formed between adjacent conductive features in the upper conductive layer.
20 . The method of claim 13 , further comprising:
planarizing an upper surface of the etching-process-free dielectric to expose the upper conductive feature prior to forming a subsequent metallization level.