IP Library Granted Patent US 12690437
Granted Patent B2
US 12690437 · App. 17/878,340 · Granted Jul 21, 2026

Semiconductor fabrication method with improved deposition quality and semiconductor structure thereof

Inventors: Rui Song (Wuhan, CN); Jie Pan (Wuhan, CN); Peng Ding (Wuhan, CN); Jiewen Zhang (Wuhan, CN); Xufang Chen (Wuhan, CN)
Assignee: Yangtze Memory Technologies Co., Ltd.
H10W20/20H10B41/27H10B43/27H10W90/00H10W80/312H10W80/327H10W90/792
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690437
App. No.
17/878,340
Granted
Jul 21, 2026
Kind
B2
Abstract

A structure includes a base layer and conductive element in a dielectric region. The base layer includes a first material and is perpendicular to a direction. The conductive element includes a conductive material and contacts the base layer and the dielectric region. An interface parallel to the direction is formed between the conductive element and the dielectric region. A deposition rate of the conductive material over a surface of the base layer is higher than that over a surface of the dielectric region.

Claims (49)

1 . A structure, comprising:

a dielectric region;

a conductive member in the dielectric region and extending along a vertical direction;

a base layer formed directly on an entire top surface of the conductive member and in the dielectric region, the base layer including a first material different than a dielectric material of the dielectric region; and

a conductive element deposited directly on the first material of the base layer and directly on sidewalls of the dielectric region, wherein

the conductive element includes a lateral dimension smaller than a lateral dimension of the base layer, and

the conductive element includes a conductive molybdenum (Mo) material having a higher deposition rate directly on the first material that includes titanium nitride (TiN), Mo, or ruthenium (Ru) than on the dielectric material of the dielectric region to provide the conductive element with reduced seams or voids there-in.

2 . The structure according to claim 1 , wherein the dielectric region includes an oxide or nitride material.

3 . The structure according to claim 1 , wherein the conductive element includes a via or a conductive line.

4 . The structure according to claim 1 , wherein the conductive member includes at least one of a word line contact, a through contact, an interconnect, a via contact, or a plug.

5 . The structure according to claim 1 , wherein the conductive Mo material is arranged for formation of the conductive element in a bottom-up manner to reduce seams or voids.

6 . A system, comprising:

a memory device; and

a memory controller for controlling the memory device, the memory device comprising a structure, the structure comprising:

a dielectric region;

a conductive member in the dielectric region and extending along a vertical direction;

a base layer formed directly on an entire top surface of the conductive member and in the dielectric region, the base layer including a first material different than a dielectric material of the dielectric region; and

a conductive element deposited directly on the first material of the base layer and directly on sidewalls of the dielectric region, wherein

the conductive element includes a lateral dimension smaller than a lateral dimension of the base layer, and

the conductive element includes a conductive molybdenum (Mo) material molybdenum (Mo) having a higher deposition rate directly on the first material that includes titanium nitride (TiN), Mo, or ruthenium (Ru) than on the dielectric material of the dielectric region to provide the conductive element with reduced seams or voids there-in.

7 . The system according to claim 6 , wherein the dielectric region includes an oxide or nitride material.

8 . The system according to claim 6 , wherein the conductive element includes a via or a conductive line.

9 . The system according to claim 6 , wherein the conductive member includes at least one of a word line contact, a through contact, an interconnect, a via contact, or a plug.

10 . The system according to claim 6 , wherein the conductive Mo material is arranged for formation of the conductive element in a bottom-up manner to reduce seams or voids.

11 . A method for fabricating a structure, comprising:

forming a conductive member in a dielectric layer;

depositing a first material to form a base layer directly on an entire top surface of the conductive member, the first material including titanium nitride (TiN), molybdenum (Mo), or ruthenium (Ru);

depositing a dielectric material to grow the dielectric layer to cover the base layer;

forming an opening through the dielectric layer to expose the base layer at a bottom of the opening; and

depositing a conductive Mo material to fill the opening, a deposition rate of the conductive Mo material over a surface of the base layer being higher than a deposition rate of the conductive Mo material over a surface of a sidewall of the opening in the dielectric layer, the conductive Mo material arranged for filling the opening with reduced seams or voids.

12 . The method according to claim 11 , wherein the dielectric material includes an oxide material or a nitride material.

13 . The method according to claim 11 , wherein depositing the conductive Mo material to fill the opening comprises:

using molybdenum pentachloride (MoCl 5 ) and hydrogen; and

performing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) to deposit the conductive material Mo to fill the opening.

14 . The method according to claim 11 , wherein depositing the conductive Mo material to fill the opening comprises:

performing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) to deposit the conductive Mo material to fill the opening in the bottom-up manner.

15 . The method according to claim 11 , wherein depositing the conductive Mo material to fill the opening includes:

depositing the conductive Mo material to form a conductive layer inside the opening at a first deposition step;

after the first deposition step, removing a portion of the conductive layer to avoid closure of the opening at a first etch step; and

after the first etch step, depositing the conductive Mo material inside the opening to grow the conductive layer to fill the opening at a second deposition step.

16 . The method according to claim 15 , wherein depositing the conductive Mo material to fill the opening further includes:

performing a second etch step to remove a part of the conductive layer to avoid closure of the opening after the second deposition step; and

performing a third deposition step to deposit the conductive Mo material inside the opening to grow the conductive layer to fill the opening after the second etch step.

17 . The method according to claim 11 , wherein the conductive Mo material is deposited inside the opening to form a via or a conductive line.

18 . The method according to claim 15 , wherein removing the portion of the conductive layer to avoid closure of the opening at the first etch step comprises:

using molybdenum pentachloride (MoCl 5 ); and

performing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) to remove the portion of the conductive layer.

19 . The method according to claim 15 , wherein removing the portion of the conductive layer to avoid closure of the opening at the first etch step comprises:

removing the conductive Mo material from the conductive layer, wherein a desorption rate of the conductive Mo material is higher in an area close to an entrance of the opening than a desorption rate of the conductive Mo material in an area at the bottom of the opening.