Inline circuit edit for backside power delivery
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer. The conductive feedthrough structure is a monolithic structure extending through the device layer.
1 . An integrated circuit structure, comprising:
a device layer comprising a plurality of transistor structures;
a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors;
a first backside metal structure below the device layer;
a conductive feedthrough structure directly coupling the first backside metal structure to the front-end routing layer, wherein the conductive feedthrough structure is a monolithic structure extending through the device layer;
a second backside metal structure coupled to one of the plurality of transistors by a backside contact structure, the second backside metal structure laterally adjacent to the first backside metal structure; and
a backside routing layer below the first backside metal structure and the second backside metal structure, the backside routing layer coupling the first backside metal structure to the second backside metal structure.
2 . The integrated circuit structure of claim 1 , wherein individual ones of the plurality of transistors include a plurality of nanowires.
3 . The integrated circuit structure of claim 1 , wherein the conductive feedthrough structure delivers power from the first backside metal structure to the front-end routing layer.
4 . The integrated circuit structure of claim 1 , wherein the conductive feedthrough structure is fabricated by an inline circuit edit process.
5 . A method of fabricating an integrated circuit structure, the method comprising:
forming a device layer comprising a plurality of transistor structures;
forming a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors;
forming a conductive feedthrough structure using a maskless lithography process, the conductive feedthrough structure coupled to the front-end routing layer;
forming a backside contact structure using a masked lithography process, the backside contact structure coupled to one of the plurality of transistors;
forming a first backside metal structure below the device layer, wherein the conductive feedthrough structure directly couples the first backside metal structure to the front-end routing layer, and forming a second backside metal structure below the device layer and laterally spaced apart from the first backside metal structure, the second backside metal structure coupled to the backside contact structure; and
forming a backside routing layer below the first backside metal structure and the second backside metal structure, the backside routing layer coupling the first backside metal structure to the second backside metal structure.
6 . The method of claim 5 , wherein the maskless lithography process is an e-beam process.
7 . The method of claim 5 , wherein the masked lithography process is an extreme ultraviolet (EUV) process.
8 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a device layer comprising a plurality of transistor structures;
a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors;
a first backside metal structure below the device layer;
a conductive feedthrough structure directly coupling the first backside metal structure to the front-end routing layer, wherein the conductive feedthrough structure is a monolithic structure extending through the device layer;
a second backside metal structure coupled to one of the plurality of transistors by a backside contact structure, the second backside metal structure laterally adjacent to the first backside metal structure; and
a backside routing layer below the first backside metal structure and the second backside metal structure, the backside routing layer coupling the first backside metal structure to the second backside metal structure.
9 . The computing device of claim 8 , further comprising:
a memory coupled to the board.
10 . The computing device of claim 8 , further comprising:
a communication chip coupled to the board.
11 . The computing device of claim 8 , wherein the component is a packaged integrated circuit die.
12 . The computing device of claim 8 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
13 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming a device layer comprising a plurality of transistor structures;
forming a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors;
forming a conductive feedthrough structure using a maskless lithography process, the conductive feedthrough structure coupled to the front-end routing layer;
forming a backside contact structure using a masked lithography process, the backside contact structure coupled to one of the plurality of transistors;
forming a first backside metal structure below the device layer, wherein the conductive feedthrough structure directly couples the first backside metal structure to the front-end routing layer, and forming a second backside metal structure below the device layer and laterally spaced apart from the first backside metal structure, the second backside metal structure coupled to the backside contact structure; and
forming a backside routing layer below the first backside metal structure and the second backside metal structure, the backside routing layer coupling the first backside metal structure to the second backside metal structure.
14 . The computing device of claim 13 , further comprising:
a memory coupled to the board.
15 . The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16 . The computing device of claim 13 , wherein the component is a packaged integrated circuit die.
17 . The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.