Semiconductor device including backside signal wiring and frontside power supply
A semiconductor device is provided including frontside interconnects (i.e., metal wires) used mainly as power supplies and backside interconnects (i.e., metal wires) used mainly as signal wiring. The semiconductor device includes a frontside back-end-of-the-line (BEOL) structure including frontside metal wires located in the frontside of the device, and a backside BEOL interconnect structure including backside metal wires located in a backside of the device. At least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires.
1 . A semiconductor device comprising:
a transistor located in a frontside of the device, the transistor including a gate structure located adjacent to a pair of source/drain regions;
a frontside BEOL structure comprising frontside metal wires located in the frontside of the device; and
a backside BEOL interconnect structure comprising backside metal wires located in a backside of the device, wherein at least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires.
2 . The semiconductor device of claim 1 , further comprising a middle-of-the- line (MOL) level located between the frontside BEOL structure and the transistor.
3 . The semiconductor device of claim 2 , wherein the MOL level comprises a frontside source/drain contact structure embedded in a MOL dielectric layer.
4 . The semiconductor device of claim 3 , wherein the frontside source/drain contact structure electrically connects one source/drain region of the pair of source/drain regions of the transistor to the frontside BEOL structure.
5 . The semiconductor device of claim 4 , further comprising a backside source/drain contact structure contacting a surface of the other source/drain region of the pair of source/drain regions of the transistor and a backside gate contact structure contacting the gate structure of the transistor.
6 . The semiconductor device of claim 5 , wherein the backside source/drain contact structure and the backside gate contact structure are both embedded in a backside interlayer dielectric layer.
7 . The semiconductor device of claim 6 , wherein the backside gate contact structure passes through a shallow trench isolation structure and the shallow trench isolation is present in the backside interlayer dielectric layer.
8 . The semiconductor device of claim 5 , wherein further comprises a first backside metal level located between backside BEOL structure and both the backside source/drain contact structure and the backside gate contact structure, wherein the first backside metal level comprises backside interconnects that electrically connect the backside BEOL structure to the backside source/drain contact structure and the backside gate contact structure, wherein the backside interconnects are signal wires.
9 . The semiconductor device of claim 8 , wherein the backside interconnects are embedded in a backside interlayer dielectric layer.
10 . The semiconductor device of claim 4 , wherein the one source/drain region of the pair of source/drain regions that is electrically connected to the frontside BEOL structure is located on a surface of a dielectric structure, the dielectric structure is present in both the frontside and the backside of the device.
11 . The semiconductor device of claim 10 , further comprising a bottom dielectric isolation layer located beneath the transistor and adjacent to the dielectric structure.
12 . The semiconductor device of claim 11 , wherein the dielectric structure contacts a sidewall of the bottom dielectric isolation layer.
13 . The semiconductor device of claim 10 , further comprising another transistor located adjacent to the transistor, wherein the another transistor comprises another gate structure, and the another transistor comprises the one source/drain region of the pair of source/drain regions that is electrically connected to the frontside BEOL structure as one of the another transistor source/drain regions.
14 . The semiconductor device of claim 13 , further comprising another backside gate contact structure contacting the another gate structure and a sidewall and a horizontal surface of the dielectric structure.
15 . The semiconductor device of claim 14 , further comprises another bottom dielectric isolation layer located beneath the another transistor, wherein the another backside gate contact structure passes through the another bottom dielectric isolation layer.
16 . The semiconductor device of claim 13 , further comprises a first backside metal level located between the backside BEOL structure and the another backside gate contact structure, wherein the first backside metal level includes a backside interconnect connecting the another backside gate contact structure to the backside BEOL structure, and the backside interconnect is a signal wire.
17 . The semiconductor device of claim 16 , wherein the backside interconnect is embedded in a backside interlayer dielectric layer.
18 . The semiconductor device of claim 1 , wherein the transistor is a nanosheet transistor comprising a vertical stack of suspended semiconductor channel material nanosheets, and wherein the gate structure of the transistor wraps around each semiconductor channel material nanosheet of the vertical stack of suspended semiconductor channel material nanosheets.
19 . A semiconductor device comprising:
a transistor located in a frontside of the device, the transistor including a gate structure located adjacent to a pair of source/drain regions;
a frontside BEOL structure comprising frontside metal wires located in the frontside of the device;
a backside BEOL interconnect structure comprising backside metal wires located in a backside of the device, wherein at least 90 % of the frontside metal wires are power distribution metal wires and at least 90 % of the backside metal wires are signal wire; and
a frontside gate contact structure connecting another gate structure of another transistor to the frontside BEOL structure, wherein the another gate structure of the another transistor is tied-off.