Semiconductor device including through via and method of making
A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.
1 . A semiconductor device comprising:
a substrate;
a conductive mesh on a first side of the substrate;
an active region on a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate;
a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate, and the through via comprises a conductive material; and
a contact structure on the second side of the substrate, wherein the contact structure is physically between the through via and the active region, the contact structure is in direct contact with the through via, the contact structure overlaps a top surface of the through via in a top view, and the contact structure directly contacts both the top surface of the conductive material of the through via and a sidewall of the conductive material of the through via.
2 . The semiconductor device of claim 1 , wherein the contact structure overlaps less than an entirety of the top surface of the through via in the top view.
3 . The semiconductor device of claim 1 , wherein the contact structure is physically between the through via and the active region.
4 . The semiconductor device of claim 1 , wherein the through via has a width, and a dimension of overlap of the contact structure over the top surface of the through via ranges from about 50% to about 80% of the width.
5 . The semiconductor device of claim 1 , further comprising a second active region, wherein the through via is between the active region and the second active region, and the through via is electrically isolated from the second active region.
6 . The semiconductor device of claim 5 , wherein the through via comprises:
a protective layer.
7 . The semiconductor device of claim 6 , wherein the protective layer is between the conductive material and the second active region.
8 . The semiconductor device of claim 6 , wherein a portion of the contact structure is in direct contact with a sidewall of the conductive material and is in direct contact with a top surface of the protection layer.
9 . The semiconductor device of claim 5 , further comprising a hardmask layer, wherein the hardmask layer is between the through via and the second active region.
10 . The semiconductor device of claim 5 , wherein a dopant type of the active region is a same dopant type as the second active region.
11 . The semiconductor device of claim 1 , wherein an entirety of the through via is offset from the active region in the top view.
12 . A semiconductor device comprising:
a substrate;
a conductive mesh on a first side of the substrate;
an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate;
a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate; and
a gate structure on the second side of the substrate, wherein the gate structure is in direct contact with the through via, the gate structure overlaps a top surface of the through via in a top view, the gate structure extends beyond a periphery of the through via in a direction parallel to a surface of the second side of the substrate, and a portion of the gate structure is closer to the conductive mesh in a direction perpendicular to the surface of the second side of the substrate than a contact location between the gate structure and the through via.
13 . The semiconductor device of claim 12 , wherein the through via comprises:
a protective layer; and
a conductive material, wherein the gate structure directly contacts the conductive material.
14 . The semiconductor device of claim 13 , wherein the protective layer is between the conductive material and the active region.
15 . The semiconductor device of claim 12 , wherein the through via has a width, and a dimension of overlap of the gate structure over the top surface of the through via ranges from about 50% to about 80% of the width.
16 . The semiconductor device of claim 12 , further comprising a second active region, wherein the active region is between the through via and the second active region, and the gate structure extends over both the active region and the second active region.
17 . A semiconductor device comprising:
a substrate;
a routing structure on a first side of the substrate;
a plurality of active regions on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate;
a through via electrically connected to the routing structure, wherein the through via extends through the substrate between adjacent active regions of the plurality of active regions; and
a contact structure on the second side of the substrate, wherein the contact structure is in direct contact with a top surface of the through via, and the contact structure is in direct contact with a sidewall of a first active region of the plurality of active regions.
18 . The semiconductor device of claim 17 , wherein the contact structure overlaps the first active region of the plurality of active regions.
19 . The semiconductor device of claim 17 , wherein the through via is electrically isolated from at least one of the plurality of active regions.
20 . The semiconductor device of claim 17 , wherein the contact structure is a gate contact, and the semiconductor device further comprises:
a second gate contact aligned with the gate contact in a first direction parallel to the second side of the substrate, and the second gate contact is spaced from the gate contact in the first direction.