Common mode suppression circuit

Inventors: Siraj Akhtar (Dallas, TX); Vineethraj Rajappan Nair (Freising, BY); Robert Taft (Freising, BY); Swaminathan Sankaran (Dallas, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H01L23/528 H01L23/5226 H01L24/08 H01L24/16 H01L24/48 H01L2224/08113 H01L2224/16054 H01L2224/16055 H01L2224/16235 H01L2224/16238 H01L2224/48225 H01L2224/48465 H01L2924/15311

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Quick Facts

Patent No.: US 12690447
App. No.: 18/107,600
Granted: Jul 21, 2026
Kind: B2

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Abstract

An integrated circuit includes a semiconductor die, a package substrate having opposite first and second surfaces, where the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad. The semiconductor die is mounted on the second metal pad and the third metal pad by respective first and second metal interconnects. The package substrate includes a circuit with a single-ended terminal and a pair of differential terminals, where the single-ended terminal coupled to the first metal pad. The backage substrate also includes a metal layer including a first meandered conductor and a second meandered conductor. The first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad. The second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.

Claims (36)

1 . An integrated circuit comprising:

a semiconductor die; and

a package substrate having opposite first and second surfaces, in which the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad, the semiconductor die mounted on the second metal pad and the third metal pad by respective first and second metal interconnects, and the package substrate including:

a circuit having a single-ended terminal and a pair of differential terminals, the single-ended terminal coupled to the first metal pad; and

a metal layer including a first meandered conductor and a second meandered conductor, in which the first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad; and the second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.

2 . The integrated circuit of claim 1 , wherein dimensions of the first and second meandered conductors are based on at least one of: an operation frequency of the circuit, or an impedance resonant frequency between the second and third metal pads.

3 . The integrated circuit of claim 2 , wherein the circuit is configured to provide first and second signals having the operation frequency at the pair of differential terminals; and

the dimensions of the first and second meandered conductors are based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

4 . The integrated circuit of claim 3 , wherein the first and second meandered conductors are configured to provide different propagation distances for the respective first and second signals; and

a difference between the propagation distances is based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

5 . The integrated circuit of claim 3 , wherein the first meandered conductor has a first width, the second meandered conductor has a second width, and a difference between the first and second widths is based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

6 . The integrated circuit of claim 1 , wherein:

the package substrate includes a first metal layer and a second metal layer;

the first meandered conductor and the second meandered conductor are in the first metal layer; and

the second metal layer includes a third conductor and a fourth conductor, the third conductor coupled between the first terminal and the second metal pad, and the fourth conductor is coupled between the second terminal and the third metal pad.

7 . The integrated circuit of claim 6 , wherein dimensions of the third and fourth conductors are based on an operation frequency of the circuit.

8 . The integrated circuit of claim 7 , wherein the circuit is configured to provide first and second signals having the operation frequency at the pair of differential terminals; and

wherein the dimensions of the third and fourth conductors are based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

9 . The integrated circuit of claim 7 , wherein:

the circuit is configured to provide first and second signals having the operation frequency at the pair of differential terminals;

the first meandered conductor overlaps at least a part of the third conductor by a first overlap area;

the second meandered conductor overlaps at least a part of the fourth conductor by a second overlap area; and

a difference between the first and second overlap areas is based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

10 . The integrated circuit of claim 8 , wherein the integrated circuit further comprises:

a metal shield overlapping at least a part of the first meandered conductor by a first overlap area;

the metal shield overlapping at least a part of the second meandered conductor by a second overlap area; and

a difference between the first and second overlap areas is based on at least one of a phase imbalance or an amplitude imbalance between the first and second signals.

11 . The integrated circuit of claim 1 , where the circuit is formed on two or more metal layers of the package substrate.

12 . The integrated circuit of claim 1 , where the circuit includes a balun.

13 . The integrated circuit of claim 12 , where:

a first side of the balun is on a first metal layer of the package substrate; and

a second side of the balun is on a second metal layer of the package substrate.

14 . The integrated circuit of claim 13 , where the first side of the balun and the second side of the balun at least partially overlap.

15 . The integrated circuit of claim 13 , where the first meandered conductor and the second meandered conductor are on a same metal layer as the first side of the balun or the second side of the balun.

16 . The integrated circuit of claim 1 , where the third first metal pad and the first and second and third metal pads are on opposite sides of the package substrate.

17 . The integrated circuit of claim 10 , where the metal shield includes a first plurality of metal teeth extensions and a second plurality of metal teeth extensions.