Memory device including source structure having conductive islands of different widths

1 . An apparatus comprising:

a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions;

conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region, each of the conductive islands including a width;

dielectric isolators separating the conductive islands from each other, wherein:

the conductive islands include a conductive island such that a first portion of the conductive islands is located on a first side of the conductive island, and a second portion of the conductive islands is located on a second side of the conductive island; and

the width of the conductive island is greater than the width of at least one conductive island in the first portion of the conductive islands and at least one conductive island in the second portion of the conductive islands, wherein one of the conductive islands in the first portion of the conductive islands includes a width greater than a width of each of the other conductive islands in the first portion of the conductive islands.

2 . The apparatus of claim 1 , further comprising;

data lines formed over the first and second memory cells; and

conductive pillars extending between the data lines and the conductive islands and coupled to the data lines and the conductive islands.

3 . The apparatus of claim 1 , wherein one of the conductive islands in the second portion of the conductive islands includes a width greater than a width of each of the other conductive islands in the second portion of the conductive islands.

4 . The apparatus of claim 1 , wherein the apparatus comprises a memory device, the memory device including circuitry located under the conductive structure and coupled to the conductive islands.

5 . An apparatus comprising:

conductive islands adjacent each other and formed in a conductive region and separated from the conductive region, each of the conductive islands including a width;

dielectric isolators separating the conductive islands from each other;

data lines for memory cells and formed over the conductive region;

conductive pillars extending between the data lines and the conductive islands and coupled to the data lines and the conductive islands, wherein:

the conductive islands include a pair of conductive islands adjacent each other such that a first portion of the conductive islands is located on a first side of the pair of conductive islands, and a second portion of the conductive islands is located on a second side of the pair of conductive islands;

the width of each conductive island of the pair of conductive islands is greater than the width of each conductive island in the first and second portions of the conductive islands:

the conductive region is part of a conductive structure, the conductive structure including a first additional region formed under a first portion of the memory cells, and a second additional region formed under a second portion of the memory cells, wherein the conductive region is between the first and second additional regions;

the first portion of the memory cells are included in a first memory block, and the second portion of the memory cells are included in a second memory cell memory block; and

the data lines are shared by the first and second memory cell blocks.

6 . The apparatus of claim 5 , wherein one of the conductive islands in the first portion of the conductive islands includes a width greater than a width of each of the other conductive islands in the first portion of the conductive islands.

7 . The apparatus of claim 6 , wherein one of the conductive islands in the second portion of the conductive islands includes a width greater than a width of each of the other conductive islands in the second portion of the conductive islands.

8 . An apparatus comprising:

a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions;

first conductive islands adjacent each other and formed in a first location of the third conductive region and separated from the third conductive region, the first conductive islands separated from each other by first dielectric isolators, each of the first conductive islands including a width, wherein the width of two of the first conductive islands is greater than the width of each of the other first conductive islands;

second conductive islands adjacent each other and formed in a second location of the third conductive region and separated from the third conductive region, the second conductive islands separated from each other by second dielectric isolators, each of the second conductive islands including a width, wherein the width of two of the second conductive islands is greater than the width of each of the other second conductive islands;

third conductive islands adjacent each other and formed in a third location of the third conductive region and separated from the third conductive region, the third conductive islands separated from each other by third dielectric isolators, each of the third conductive islands including a width, wherein the width of two of the third conductive islands is greater than the width of each of the other third conductive islands;

fourth conductive islands adjacent each other and formed in a fourth location of the third conductive region and separated from the third conductive region, the fourth conductive islands separated from each other by fourth dielectric isolators, each of the fourth conductive islands including a width, wherein the width of two of the fourth conductive islands is greater than the width of each of the other fourth conductive islands, wherein:

the third conductive region includes a first conductive portion between the first and third locations, a second conductive portion between the second and fourth locations, and a third conductive portion between the first and second conductive portions and in electrical contact with the first and second conductive portions.

9 . The apparatus of claim 8 , wherein a total number of each of the first, second, third, and fourth conductive islands is an even number.

10 . The apparatus of claim 8 , further comprising:

first dummy memory cells over the first conductive portion; and

second dummy memory cells over the second conductive portion.

11 . The apparatus of claim 8 , further comprising data lines over the conductive structure and coupled to the first, second, third, and fourth conductive islands.

12 . An apparatus comprising:

a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions;

conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region; and

dielectric isolators separating the conductive islands from each other, each of the dielectric isolators including a width, wherein the width of one of the dielectric isolators is at least one and a half times greater than the width of each remaining dielectric isolator among the dielectric isolator, wherein:

the dielectric isolators include a dielectric isolator such that a first one-half of a total number of the conductive islands is located on a first side of the dielectric isolator, a second one-half of the total number of the conductive islands is located on a second side of the dielectric isolator; and

the dielectric isolator has a width at least two times greater than the width of each dielectric isolator between adjacent conductive islands of each of the first one-half and the second one-half of the total number of the conductive islands.

13 . The apparatus of claim 12 , wherein a total number of the conductive islands is an even number.

14 . The apparatus of claim 12 , wherein a total number of the dielectric isolators is an odd number.

15 . The apparatus of claim 12 , further comprising data lines over the first memory cells and coupled to the conductive islands.

16 . The apparatus of claim 12 , wherein the dielectric isolators include:

first dielectric isolators separating the conductive islands on the first side of the dielectric isolator from each other;

second dielectric isolators separating the conductive islands on the second side of the dielectric isolator from each other; and

one of the first dielectric isolators includes a width greater than a width of each dielectric isolator of a remaining portion of the first dielectric isolators.

17 . The apparatus of claim 16 , wherein one of the second dielectric isolators includes a width greater than a width of each dielectric isolator of a remaining portion of the second dielectric isolators.

18 . An apparatus comprising:

a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions;

first conductive islands adjacent each other and formed in a first location of the third conductive region and separated from the third conductive region;

first dielectric isolators separating the conductive islands from each other, each of the dielectric isolators including a width, wherein the width of one of the first dielectric isolators is at least two times greater than the width of each of the other first dielectric isolators;

second conductive islands adjacent each other and formed in a second location of the third conductive region and separated from the third conductive region, the second location adjacent the first location in a first direction;

second dielectric isolators separating the second conductive islands from each other, each of the second dielectric isolators including a width, wherein the width of one of the second dielectric isolators is at least two times greater than the width of each of the other second dielectric isolators;

third conductive islands adjacent each other and formed in a third location of the third conductive region and separated from the third conductive region, the third location adjacent the first location in a second direction;

third dielectric isolators separating the third conductive islands from each other, each of the third dielectric isolators including a width, wherein the width of one of the third dielectric isolators is at least two times greater than the width of each of the other the third dielectric isolators;

fourth conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region, the fourth location adjacent the third location in the first direction;

fourth dielectric isolators separating the conductive islands from each other, each of the dielectric isolators including a width, wherein the width of one of the fourth dielectric isolators is at least two times greater than the width of each of the other fourth dielectric isolators, wherein:

the third conductive region includes a first conductive portion between the first and third locations, a second conductive portion between the second and fourth locations, and a third conductive portion between the first and second conductive portions and in electrical contact with the first and second conductive portions.

19 . The apparatus of claim 18 , wherein a total number of each of the first, second, third, and fourth dielectric isolators is an odd number.

20 . The apparatus of claim 18 , further comprising:

first dummy memory cells over the first conductive portion; and

second dummy memory cells over the second conductive portion.

21 . The apparatus of claim 18 , further comprising data lines over the conductive structure and coupled to the first, second, third, and fourth conductive islands.