Semiconductor device and fabricating method thereof
View Patent ↗The present disclosure provides a semiconductor device and a fabricating method thereof, and the semiconductor device includes a substrate, a plurality of conductive pads, and a plurality of conductive columns. The conductive pads are separately disposed in a first insulating layer, over the substrate. The conductive columns are separately disposed in a second insulating layer, individually contacting each of the conductive pads. The second insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked on sidewalls of the conductive columns, wherein the second dielectric layer physically contacts the first dielectric layer, the conductive pads and the third dielectric layer at the same time. The second insulating layer is allowable to avoid the short-circuit issue caused by excessively lateral etching, thereby improving the structural reliability and the performances.
1 . A semiconductor device, comprising:
a substrate;
a stack layer structure, disposed on the substrate and comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked with each other;
a plurality of conductive pads, separately disposed in a first insulating layer and disposed over the substrate; and
a plurality of conductive columns, separately disposed in the stack layer structure and a second insulating layer, the conductive columns respectively contacting each of the conductive pads, and the second insulating layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer stacked on sidewalls of each of the conductive columns, wherein the second dielectric layer physically contacts the first dielectric layer, the conductive pads and the third dielectric layer at the same time, and the stack layer structure directly contacts a sidewall of the first dielectric layer.
2 . The semiconductor device according to claim 1 , wherein a bottom surface of the second dielectric layer and a bottom surface of the conductive columns are coplanar with each other.
3 . The semiconductor device according to claim 1 , wherein the second dielectric layer is sandwiched between the first dielectric layer and the third dielectric layer.
4 . The semiconductor device according to claim 1 , wherein the second dielectric layer is enclosed by the first dielectric layer, the conductive pads and the third dielectric layer.
5 . The semiconductor device according to claim 1 , wherein the second insulating layer further comprises a fourth dielectric layer stacked on the third dielectric layer, and an inner sidewall of the second dielectric layer is vertically aligned with a sidewall of the fourth dielectric layer.
6 . The semiconductor device according to claim 1 , wherein an extension area of the second dielectric layer in a horizontal direction is smaller than an extension area of each of the conductive pads in the horizontal direction.
7 . The semiconductor device according to claim 1 , wherein materials of the third dielectric layer, the second dielectric layer and the first dielectric layer are all different from each other, the first dielectric layer comprises a high-k dielectric material, and the material of the third dielectric layer is the same as a material of the first insulating layer.
8 . The semiconductor device according to claim 7 , wherein the second dielectric layer comprises a metal-oxide material.
9 . The semiconductor device according to claim 5 , wherein the second dielectric layer and the first dielectric layer respectively comprises a L-shape cross-section, and a horizontal portion of the L-shape cross-section of the first dielectric layer and a horizontal portion of the L-shape cross-section of the second dielectric layer both comprise inner sidewalls being vertically aligned with each other.
10 . The semiconductor device according to claim 9 , wherein the L-shape cross-section of the first dielectric layer comprises a vertical portion being vertically aligned with a sidewall of the fourth dielectric layer.
11 . The semiconductor device according to claim 1 , wherein the second dielectric layer comprises a gyro-shaped recess or a dish-shaped recess, and the first dielectric layer conformally covers the gyro-shaped recess or a dish-shaped recess of the second dielectric layer.
12 . A semiconductor device, comprising:
a substrate;
a first insulating layer, a second insulating layer, and a stack layer structure respectively disposed on the substrate from bottom to top, wherein the stack layer structure comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked with each other;
a plurality of conductive pads, separately disposed in the first insulating layer;
a plurality of conductive columns, separately disposed in the stack layer structure and in second insulating layer, the conductive columns respectively contacting the conductive pads;
a first dielectric layer disposed between the conductive columns and the second insulating layer, wherein a bottom surface of the first dielectric layer is coplanar with a bottom surface of the second insulating layer, and the bottom surface of the second insulating layer directly contacts top surfaces of the contact pads and the first insulating layer; and
a second dielectric layer disposed between the stack layer structure and the conductive columns, and between the first dielectric layer and the conductive columns.
13 . The semiconductor device according to claim 12 , wherein a top surface of the first dielectric layer is not higher than the top surface of the second insulating layer.
14 . The semiconductor device according to claim 12 , wherein the first dielectric layer comprises a L-shaped cross-section.
15 . A semiconductor device, comprising:
a substrate; and
a plurality of conductive columns, separately disposed in an insulating layer, and disposed over the substrate;
wherein the insulating layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer stacked on sidewalls of each of the conductive columns;
wherein, the second dielectric layer and the first dielectric layer respectively comprises a L-shape cross-section, and a horizontal portion of the L-shape cross-section of the first dielectric layer and a horizontal portion of the L-shape cross-section of the second dielectric layer both comprise inner sidewalls being vertically aligned with each other.