Staircase structure in three-dimensional memory device and method for forming the same
In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs extending along a first lateral direction. The plurality of stairs include a stair including a conductor portion on a top surface of the stair. The conduction portion is connected to the memory array structure. Widths of conductor portions are different in a second lateral direction perpendicular to the first lateral direction.
1 . A three-dimensional (3D) memory device, comprising:
a memory array structure; and
a staircase structure comprising a plurality of stairs extending along a first lateral direction, wherein a stair of the plurality of stairs comprises a conductor portion on a top surface of the stair and a dielectric layer, the conductor portion being connected to the memory array structure,
wherein:
in the stair of the plurality of stairs, a width of the conductor portion, in the first lateral direction, varies along a second lateral direction perpendicular to the first lateral direction;
the conductor portion extends laterally to connect a conductor layer of the memory array structure at a same vertical level as the conductor portion; and
in the second lateral direction, a dielectric portion is adjacent to an end of the conductor portion at the same vertical level, and the dielectric layer extends continuously below the dielectric portion and the conductor portion.
2 . The 3D memory device of claim 1 , wherein a thickness of the conductor portion is equal to or less than a thickness of the dielectric portion along a vertical direction perpendicular to the first and second lateral directions.
3 . The 3D memory device of claim 1 , wherein a thickness of the dielectric layer is less than the dielectric portion along a vertical direction perpendicular to the first and second lateral directions.
4 . The 3D memory device of claim 1 , wherein each of the conductor portion and the dielectric layer is above one or more dielectric pairs.
5 . The 3D memory device of claim 1 , wherein a portion of the conductor portion overlaps with an upper stair.
6 . The 3D memory device of claim 5 , wherein the portion of the conductor portion has a lateral shape of a right triangle.
7 . The 3D memory device of claim 1 , wherein:
the dielectric portion is a first dielectric portion; and
the stair of the plurality of stairs further comprises a second dielectric portion adjacent to the first dielectric portion, and the second dielectric portion surrounds a sidewall of the conductor portion along the second lateral direction, the first dielectric portion, the second dielectric portion, and the conductor portion having a same thickness in a vertical direction perpendicular to the first and second lateral directions.
8 . The 3D memory device of claim 7 , wherein the dielectric layer extends continuously below the second dielectric portion.
9 . A three-dimensional (3D) memory device, comprising:
a memory array structure; and
a staircase structure comprising a plurality of stairs extending along a first lateral direction, wherein a stair of the plurality of stairs comprises a conductor portion on a top surface of the stair and a dielectric layer, the conductor portion being connected to the memory array structure,
wherein:
widths of conductor portions in a second lateral direction perpendicular to the first lateral direction decrease along the first lateral direction away from the memory array structure;
the conductor portion extends laterally to connect a conductor layer of the memory array structure at a same vertical level as the conductor portion; and
in the second lateral direction, a dielectric portion is adjacent to an end of the conductor portion at the same vertical level, and the dielectric layer extends continuously below the dielectric portion and the conductor portion.
10 . The 3D memory device of claim 9 , wherein a thickness of the dielectric layer is less than a thickness of the dielectric portion in a vertical direction perpendicular to the first and second lateral directions.
11 . The 3D memory device of claim 9 , wherein
the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicides, or polysilicon; and
the dielectric portion comprises silicon nitride.
12 . A three-dimensional (3D) memory device, comprising:
a first memory array structure;
a second memory array structure; and
a staircase structure in an intermediate of the first memory array structure and the second memory array structure each comprising a plurality of memory cells and located at one side of the staircase structure along a first lateral direction, the staircase structure comprising a plurality of stairs extending along the first lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure,
wherein:
a stair of the plurality of stairs comprises a conductor portion on a top surface of the stair and a dielectric layer, and is connected to the first memory array structure and the second memory array structure through the bridge structure;
the conductor portion extends laterally to connect a conductor layer of one of the first memory array structure or the second memory array structure at a same vertical level as the conductor portion; and
in a second lateral direction perpendicular to the first lateral direction, a dielectric portion is adjacent to an end of the conductor portion at the same vertical level, and the dielectric layer extends continuously below the dielectric portion and the conductor portion.
13 . The 3D memory device of claim 12 , wherein the conductor portion is connected to a first word line portion of the first memory array structure and a second word line portion of the second memory array structure at the same vertical level through the bridge structure.
14 . The 3D memory device of claim 13 , wherein the bridge structure comprises a plurality of conductive layers, and each of the conductive layers is in contact with the first word line portion and the second word line portion.
15 . The 3D memory device of claim 12 , wherein:
the dielectric portion is a first dielectric portion; and
in the second lateral direction, a length of the conductor portion is less than a length of a second dielectric portion that is adjacent to the first dielectric portion and surrounds a sidewall of the conductor portion along the second lateral direction.
16 . The 3D memory device of claim 15 , wherein the dielectric layer extends continuously below the second dielectric portion.
17 . The 3D memory device of claim 12 , wherein
the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicides, or polysilicon; and
the dielectric portion comprises silicon nitride.
18 . The 3D memory device of claim 12 , wherein the dielectric layer is underlying and in contact with the conductor portion and the dielectric portion, the dielectric layer comprising silicon oxide.
19 . The 3D memory device of claim 12 , wherein:
the dielectric portion is a first dielectric portion; and
the stair of the plurality of stairs further comprises a second dielectric portion adjacent to the first dielectric portion, and the second dielectric portion surrounds a sidewall of the conductor portion along the second lateral direction, the first dielectric portion, the second dielectric portion, and the conductor portion having a same thickness in a vertical direction perpendicular to the first and second lateral directions.
20 . The 3D memory device of claim 19 , wherein the dielectric layer extends continuously below the second dielectric portion.