Double-sided heat dissipation power semiconductor module and method of manufacturing the same
The present disclosure relates to a power semiconductor module of which heat is dissipated by its both sides and provides a power semiconductor module technology in which a mold is formed in a surrounding space of a power semiconductor die, and then, wires are formed on upper and lower sides of the power semiconductor die and substrates are disposed on upper and lower sides of the wires.
1 . A power semiconductor module comprising:
a semiconductor die layer in which a first power semiconductor die and a second power semiconductor die are disposed and a first mold is formed to surround lateral sides of the first power semiconductor die and the second power semiconductor die;
a wiring layer comprising a first wire disposed on an upper surface of the semiconductor die layer and a second wire disposed on a lower surface of the semiconductor die layer; and
a substrate layer configured to dissipate heat that is delivered from the semiconductor die layer to the wiring layer,
wherein the wiring layer is arranged in contact with the upper and lower surfaces of the first power semiconductor die, the second power semiconductor die, and the first mold, respectively, and
wherein a horizontal width of the wiring layer is greater than a sum of the horizontal widths of the first power semiconductor die and the second power semiconductor die.
2 . The power semiconductor module of claim 1 further comprising a second mold configured to fill a surrounding space of the wiring layer, wherein the first mold and the second mold are formed of an identical substance and are formed at different times.
3 . The power semiconductor module of claim 1 further comprising a second mold configured to fill a surrounding space of the wiring layer, wherein the first mold and the second mold are formed of an epoxy molding compound (EMC).
4 . The power semiconductor module of claim 1 , wherein:
the substrate layer comprises a first substrate disposed on one side of the wiring layer and a second substrate disposed on the other side of the wiring layer,
wherein each of the first substrate and the second substrate comprises an insulating substance layer, a heat dissipation metal layer disposed on one side of the insulating substance layer and a metal wiring layer disposed on the other side of the insulating substance layer.
5 . The power semiconductor module of claim 1 , wherein the wiring layer is longer than the substrate layer and the power semiconductor module further comprises a lead frame connected to a part of the wiring layer, which does not overlap with the substrate layer.
6 . The power semiconductor module of claim 5 , wherein the thickness of the first mold is less than the thickness of each of the first power semiconductor die and the second power semiconductor die.
7 . The power semiconductor module of claim 1 , wherein the first wire and the second wire are formed of a Cu-based metal.
8 . The power semiconductor module of claim 1 , further comprising a connection wire electrically connected at least one of the first wire and the second wire.
9 . The power semiconductor module of claim 8 , wherein the first mold comprises a first through hole penetrating the first mold, and
wherein the connection wire is disposed in the first through hole.
10 . The power semiconductor module of claim 1 , wherein the horizontal width of the wiring layer is greater than a horizontal width of the substrate layer.
11 . A power semiconductor module comprising:
a semiconductor die layer in which a first power semiconductor die and a second power semiconductor die are disposed and a first mold is formed to surround sides of the first power semiconductor die and the second power semiconductor die;
a wiring layer comprising a first wire disposed on an upper surface of the semiconductor die layer and a second wire disposed on a lower surface of the semiconductor die layer, wherein at least one of the first wire and the second wire is electrically connected through a connection wire that penetrates the first mold; and
a substrate layer configured to dissipate heat that is delivered from the semiconductor die layer to the wiring layer,
wherein the wiring layer is arranged in contact with the upper and lower surfaces of the first power semiconductor die, the second power semiconductor die, and the first mold, respectively, and
wherein a horizontal width of the wiring layer is greater than a sum of the horizontal widths of the first power semiconductor die and the second power semiconductor die.
12 . The power semiconductor module of claim 11 , further comprising a lead frame having one side, which is in contact with the wiring layer and the other side provided as an external connection terminal.
13 . The power semiconductor module of claim 12 , further comprising a second mold surrounding the one side of the lead frame.
14 . The power semiconductor module of claim 12 , wherein the lead frame is in contact with wires that are electrically connected to the connection wire on an upper side and a lower side of the wiring layer.
15 . The power semiconductor module of claim 11 , wherein:
the substrate layer comprises a first substrate disposed on an upper side of the wiring layer and a second substrate disposed on a lower side of the wiring layer,
wherein each of the first substrate and the second substrate comprises an insulating substance layer formed of a ceramic substance, a heat dissipation metal layer disposed on one side of the insulating substance layer and formed of a Cu-based metal, and a metal wiring layer disposed on the other side of the insulating substance layer and formed of a Cu-based metal.
16 . The power semiconductor module of claim 11 , wherein the first power semiconductor die and the second power semiconductor die are metal oxide semiconductor field effect transistors (MOSFETs).
17 . The power semiconductor module of claim 16 , wherein a power semiconductor die in a diode form is further disposed in the semiconductor die layer.
18 . The power semiconductor module of claim 11 , wherein the horizontal width of the wiring layer is greater than a horizontal width of the substrate layer.