IC package with very thin vapor chamber for heat dissipation

Inventor: Wei-Lin Chen (New Taipei City, TW)

Assignees: Wei-Lin Chen; Ming-Yuan Kang

H10W40/73 H10W40/778 H10W74/127

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Quick Facts

Patent No.: US 12690458
App. No.: 18/223,741
Granted: Jul 21, 2026
Kind: B2

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Abstract

An IC package comprises a substrate; a semiconductor die with a top surface, wherein the semiconductor die is stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and an encapsulating case encapsulating the substrate, the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the encapsulating case, and the distal portion of the vapor chamber extends from a wall of the encapsulating case.

Claims (26)

1 . An IC package, comprising:

a substrate; a semiconductor die with a top surface, the semiconductor die stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and an encapsulating case at least encapsulating the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the encapsulating case, and the distal portion of the vapor chamber extends out of the encapsulating case from an external wall of the encapsulating case, the proximal portion of the vapor chamber is sealed within the encapsulating case, and the distal portion of the vapor chamber is not sealed within the encapsulating case; wherein the encapsulating case is made of molding compound material, the proximal portion of the vapor chamber is sealed by the molding compound material, and there is no molding compound material between the vapor chamber and the semiconductor die, and on the distal portion.

2 . The IC package in claim 1 , wherein the vapor chamber is a thin vapor chamber with a thickness of 0.3~0.6 mm.

3 . The IC package in claim 1 , wherein, the vapor chamber is a thin vapor chamber with a thickness less than 1 mm.

4 . The IC package in claim 3 , wherein the proximal portion covers the top surface of the semiconductor die, and the vapor chamber is stacked over the semiconductor die through a TIM or thermal adhesive layer.

5 . The IC package in claim 4 , wherein a supporting pillar is between the vapor chamber and the substrate, and a height of the supporting pillar is larger than that of the semiconductor die.

6 . The IC package in claim 1 , wherein the vapor chamber comprises:

a set of isolating structures formed in the vapor chamber; and

a capillary structure formed in the vapor chamber and disposed between the set of isolating structures.

7 . The IC package in claim 6 , wherein the set of isolating structures extend along a direction from the distal portion to the proximal portion, and the set of isolating structures penetrates through the wall of the encapsulating case.

8 . The IC package in claim 6 , wherein the vapor chamber further comprises a set of supporting structures in the vapor chamber and connected to the set of isolating structures, wherein the set of supporting structures extend downward from a top side of the vapor chamber and the set of isolating structures extend upward from a bottom side of the vapor chamber, and another capillary structure is disposed between the set of supporting structures.

9 . The IC package in claim 1 , wherein the distal portion of the vapor chamber is thermally coupled to a heat sink, wherein the heat sink or the liquid is located outside the encapsulating case.

10 . The IC package in claim 1 , wherein a width of the distal portion is larger than that of the proximal portion.

11 . The IC package in claim 1 , wherein a thickness of the distal portion is larger than that of the proximal portion.

12 . An IC package, comprising: a first semiconductor chip with a top surface; a first vapor chamber stacked over the first semiconductor chip, wherein the first vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the first semiconductor chip, and a thickness of the proximal portion is less than 1 mm; and a molding compound encapsulating the first semiconductor chip and the first vapor chamber, wherein the proximal portion of the first vapor chamber is sealed within the molding compound, and the distal portion of the first vapor chamber protrudes outside of the molding compound from an external wall of the molding compound, without molding compound on the distal portion.

13 . The IC package in claim 12 , wherein a thickness of the proximal portion is between 0.2~0.8 mm.

14 . The IC package in claim 12 , wherein the first vapor chamber further comprises another distal portion protruding from another wall of the molding compound, and the proximal portion is between the distal portion and the another distal portion.

15 . The IC package in claim 12 , further comprising:

a second vapor chamber physically spaced apart from the first vapor chamber and stacked over the second semiconductor chip, wherein the second vapor chamber is encapsulated by the molding compound;

wherein the second vapor chamber comprises a proximal portion and a distal portion, the proximal portion of the second vapor chamber covers the top surface of the second semiconductor chip, and a thickness of the proximal portion of the second vapor chamber is less than 1 mm, and the distal portion of the second vapor chamber protrudes from another wall of the molding compound.

16 . An IC package, comprising: a substrate; a first semiconductor IC with a top surface, the first semiconductor IC stacked above the substrate; a first vapor chamber, wherein the first vapor chamber comprises a proximal portion and a distal portion, the proximal portion is thermally coupled to the top surface of the first semiconductor IC; and a molding compound encapsulating the first semiconductor IC and the first vapor chamber, wherein the proximal portion of the first vapor chamber is encapsulated within the molding compound, and the distal portion of the first vapor chamber protrudes outside of the molding compound from an external wall of the molding compound, without the molding compound on the distal portion; wherein the distal portion of the first vapor chamber is thermally coupled to a heat sink or a liquid pipe, wherein the heat sink or the liquid pipe is located outside the molding compound.

17 . The IC package in claim 16 , further comprising:

a second semiconductor IC with a top surface, the second semiconductor IC horizontally spaced apart from the first semiconductor IC and stacked above the substrate, wherein the second semiconductor IC is encapsulated by the molding compound.

18 . An IC package comprising:

a substrate; a semiconductor die with a top surface, the semiconductor die stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and a molding compound at least encapsulating the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the molding compound, and the distal portion of the vapor chamber extends out of a wall of the molding compound, the proximal portion of the vapor chamber is sealed within the molding compound, and the distal portion of the vapor chamber is not sealed within the molding compound, without the molding compound on the distal portion; and another vapor chamber physically spaced apart from the vapor chamber and stacked over a second semiconductor chip; wherein the another vapor chamber comprises a proximal portion and a distal portion, the proximal portion of the other vapor chamber covers the top surface of the second semiconductor chip, and the distal portion of the other vapor chamber extends out of another wall of the molding compound, without the molding compound on the distal portion.

19 . An IC package, comprising: a substrate; a semiconductor die with a top surface, the semiconductor die stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and a molding compound at least encapsulating the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the molding compound, and the distal portion of the vapor chamber extends out of a wall of the molding compound, the proximal portion of the vapor chamber is sealed within the molding compound, and the distal portion of the vapor chamber is not sealed within the encapsulating ease-molding compound, without the molding compound on the distal portion.