Semiconductor wafer

1 . A semiconductor wafer ( 1 a , 1 b ) comprising a plurality of chips ( 2 ) and a separation zone ( 3 ) spacing the semiconductor chips ( 2 ) from each other in this wafer ( 1 a , 1 b ), such a separation zone ( 3 ) extending, along a first direction, from a front face ( 4 a ) to an opposite backside face ( 4 b ) of this wafer ( 1 a , 1 b ), this separation zone ( 3 ) includes a scribe line ( 6 ) configured to be diced using plasma etching and an inlet area ( 13 ) of this scribe line ( 6 ), the inlet ( 13 ) being delimitated by free ends of plasma etch-resistant material layers ( 9 ) extending each from a peripheral wall of a functional part ( 18 ) of a chip ( 2 ) into the scribe line ( 6 ) by overlapping a top of a seal ring ( 7 ) of this chip ( 2 ), and wherein, along the first direction, at least part of each of the plurality of chips ( 2 ) is extended further from the backside face ( 4 b ) than is any portion of the plasma etch-resistant material layers ( 9 ) that is, of the plasma etch-resistant material layers ( 9 ), furthest from the backside face ( 4 b ).

2 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the separation zone ( 3 ) comprises a passivation layer ( 8 ) hermetically sealing the inlet area ( 13 ) of the scribe line ( 6 ).

3 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the separation zone ( 3 ) comprises a passivation layer ( 8 ) having a first width (W 1 ) which is less than a second width (W 3 ) separating the seal rings ( 7 ) included in the scribe line ( 6 ).

4 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the separation zone ( 3 ) comprises a passivation layer ( 8 ) hermetically linking together the free ends of plasma etch-resistant material layers ( 9 ) of the chips ( 2 ).

5 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein each plasma etch-resistant material layer ( 9 ) is formed by two parts, a first part comprising the free end protruding from the peripheral wall of the functional part ( 18 ) of each chip ( 2 ) and a second part completely included in this functional part ( 18 ).

6 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein each plasma etch-resistant material layer ( 9 ) is formed by two parts, a first part comprising the free end protruding from the peripheral wall of the functional part ( 18 ) of each chip ( 2 ) and a second part completely included in this functional part ( 18 ), the first part being protrude from the peripheral wall into the scribe line ( 6 ) by overlapping a top of the seal ring ( 7 ) of this chip ( 2 ).

7 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein a first part of the plasma etch-resistant material layer ( 9 ) protrudes from the peripheral wall into the scribe line ( 6 ) by having a lower face arranged above a top layer of the seal ring ( 7 ) of this chip ( 2 ).

8 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein a first part of the plasma etch-resistant material layer ( 9 ) protrudes from the peripheral wall into the scribe line ( 6 ) by having a lower face connected to an interconnected metal components ( 15 ) of a seal ring ( 7 ) of this chip ( 2 ).

9 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein a part of the plasma etch-resistant material layer ( 9 ) is comprised in an upper part ( 16 ) of the peripheral wall of the functional part ( 18 ) of each chip ( 2 ).

10 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein a first part of the plasma etch-resistant material layer ( 9 ) is comprised in an upper part ( 17 ) of a lateral zone of the scribe line ( 6 ), the upper part ( 17 ) being joined to the upper part ( 16 ) of the peripheral wall of a functional part ( 18 ) of each chip ( 2 ).

11 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the plasma etch-resistant material layer ( 9 ) of each chip ( 2 ) is set up to cooperate with plasma etch-resistant material layers ( 9 ) of its neighboring chips ( 2 ) to define the inlet area ( 13 ) of the scribe line ( 6 ).

12 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the scribe line ( 6 ) contains a material stack configured to be diced using plasma etching.

13 . The wafer ( 1 a , 1 b ) according to claim 1 , further comprising a passivation layer ( 11 ) covering a part of an upper surface ( 12 a ) of each chip ( 2 ) exposed to the environment.

14 . The wafer ( 1 a , 1 b ) according to claim 1 , further comprising a layer of material partially resistant ( 10 ) to plasma etching covering a passivation layer ( 11 ) arranged over a part of an upper surface ( 12 a ) of each chip ( 2 ) exposed to the environment.

15 . The wafer ( 1 a , 1 b ) according to claim 1 , wherein the semiconductor chip ( 2 ) is a RFID chip, a NFC chip and/or a Bluetooth chip.

16 . The wafer ( 1 a , 1 b ) according to claim 1 , further comprising a passivation layer ( 8 ) and a layer of material partially resistant ( 10 ) to plasma etching covering the passivation layer ( 11 ), wherein the passivation layer ( 8 ), the plasma etch-resistant material layer ( 9 ) and the layer of material partially resistant ( 10 ) are made from different materials.

17 . The wafer ( 1 a , 1 b ) according to claim 2 , wherein

the free ends of the plasma etch-resistant material layers ( 9 ) are extended, starting at first ends of the free ends, each from the peripheral wall of a functional part ( 18 ) of the chip ( 2 ) into, and to second ends of the free ends, the scribe line ( 6 ),

the first ends and the second ends are opposite ends of the plasma etch-resistant material layers ( 9 ), and

the plasma etch-resistant material layers ( 9 ) are terminated at the first ends and the second ends.

18 . The wafer ( 1 a , 1 b ) according to claim 17 , wherein

along the first direction, ends of the passivation layer ( 8 ) overlap the second ends of the free ends,

the free ends are opposite ends of the plasma etch-resistant material layers ( 9 ),

the ends of the passivation layer ( 8 ) are opposite ends of the passivation layer ( 8 ) along a second direction, perpendicular to the first direction, and

the free ends of the plasma etch-resistant material layers ( 9 ) are ones of opposite ends of the plasma etch-resistant material layers ( 9 ) along the second direction.

19 . The wafer ( 1 a , 1 b ) according to claim 14 , wherein the plasma etch-resistant material layers ( 9 ) are closer to the front face ( 4 a ) than to the opposite backside face ( 4 b ) and are partly covered:

at first ends thereof, by both ones of first passivation layers ( 11 ) and ones of layers of material partially resistant ( 10 ) to plasma etching covering the ones of the first passivation layers ( 11 ), and

at second ends thereof, by a second passivation layer ( 8 ) that is separated, along a second direction perpendicular to the first direction, from each of the first passivation layers ( 11 ).