Stress-reducing dielectric-to-metal adhesion architecture for electronic packages
An electronic device package comprises a conductive feature over a first surface of a package substrate, the conductive feature to couple to an integrated circuit die; a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen; a second dielectric layer over the first dielectric layer and having a second thickness different than the first thickness and comprising silicon and nitrogen; and a third dielectric layer over the second dielectric layer and comprising an organic material.
1 . A device, comprising:
a package substrate with a first surface;
a conductive feature over the first surface and arranged to couple to an integrated circuit die;
a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thickness different than the first thickness and comprising silicon and nitrogen; and
a third dielectric layer over the second dielectric layer and comprising an organic material, wherein the thicker of the first dielectric layer and the second dielectric layer is in contact with whichever of the conductive feature and the third dielectric layer has a lower coefficient of thermal expansion (CTE).
2 . The device of claim 1 , wherein the first thickness is not less than 250 nm and the second thickness is not more than 70 nm.
3 . The device of claim 1 , wherein at least a portion of the first dielectric layer proximal to the second dielectric layer has a columnar microstructure, and wherein the second dielectric layer is substantially amorphous.
4 . The device of claim 1 , wherein the first dielectric layer and the second dielectric layer have at least one of: (1) different compositions of SiN x and (2) different compositions among SiN x , SiO 2 , SiO x N y , and TiN.
5 . The device of claim 1 , wherein a difference in CTEs between the first dielectric layer and the second dielectric layer is substantially the same as a difference in CTEs between the conductive feature and the third dielectric layer.
6 . The device of claim 1 , wherein the first dielectric layer and the second dielectric layer have CTEs in a range of 2 to 6 ppm/K.
7 . The device of claim 1 , further comprising one or more fourth dielectric layers placed under, on, or between the first dielectric layer and the second dielectric layer and having a composition, thickness, or microstructure different than the first dielectric layer and the second dielectric layer.
8 . The device of claim 1 , further comprising:
a board coupled to the package substrate.
9 . A device, comprising:
a package substrate with a first surface;
a conductive feature over the first surface and arranged to couple to an integrated circuit die;
a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thickness different than the first thickness and comprising silicon and nitrogen; and
a third dielectric layer over the second dielectric layer and comprising an organic material, wherein the first dielectric layer has a coefficient of thermal expansion (CTE) of 2-4 ppm/K and the second dielectric layer has a CTE of 5-7 ppm/K.
10 . The device of claim 9 , wherein the first thickness is not less than 250 nm and the second thickness is not more than 70 nm.
11 . The device of claim 9 , wherein at least a portion of the first dielectric layer proximal to the second dielectric layer has a columnar microstructure, and wherein the second dielectric layer is substantially amorphous.
12 . The device of claim 9 , wherein the first dielectric layer and the second dielectric layer have at least one of: (1) different compositions of SiN x and (2) different compositions among SiN x , SiO 2 , SiO x N y , and TiN.
13 . The device of claim 9 , wherein CTEs of both the first dielectric layer and the second dielectric layer are either both smaller or both larger than the CTEs of the conductive feature and the third dielectric layer.
14 . The device of claim 9 , further comprising one or more fourth dielectric layers placed under, on, or between the first dielectric layer and the second dielectric layer and having a composition, thickness, or microstructure different than the first dielectric layer and the second dielectric layer.
15 . The device of claim 9 , further comprising:
a board coupled to the package substrate.
16 . A device, comprising:
a package substrate with a first surface;
a conductive feature over the first surface and arranged to couple to an integrated circuit die;
a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thickness different than the first thickness and comprising silicon and nitrogen; and
a third dielectric layer over the second dielectric layer and comprising an organic material, wherein the first dielectric layer has a first average grain size and the second dielectric layer has a second average grain size less than the first average grain size.
17 . The device of claim 16 , wherein the first thickness is not less than 250 nm and the second thickness is not more than 70 nm.
18 . The device of claim 16 , wherein the first dielectric layer and the second dielectric layer have at least one of: (1) different compositions of SiN x and (2) different compositions among SiN x , SiO 2 , SiO x N y , and TiN.
19 . The device of claim 16 , wherein the first dielectric layer and the second dielectric layer have coefficients of thermal expansion (CTEs) in a range of 2 to 6 ppm/K.
20 . The device of claim 16 , further comprising one or more fourth dielectric layers placed under, on, or between the first dielectric layer and the second dielectric layer and having a composition, thickness, or microstructure different than the first dielectric layer and the second dielectric layer.
21 . The device of claim 16 , further comprising:
a board coupled to the package substrate.
22 . A device, comprising:
a package substrate with a first surface;
a conductive feature over the first surface and arranged to couple to an integrated circuit die;
a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second thickness different than the first thickness and comprising silicon and nitrogen; and
a third dielectric layer over the second dielectric layer and comprising an organic material, wherein the first dielectric layer and the second dielectric layer have different microstructures among amorphous nanocolumnar and crystalline.
23 . The device of claim 22 , wherein the first thickness is not less than 250 nm and the second thickness is not more than 70 nm.
24 . The device of claim 22 , wherein the first dielectric layer and the second dielectric layer have at least one of: (1) different compositions of SiN x and (2) different compositions among SiN x , SiO 2 , SiO x N y , and TiN.
25 . The device of claim 22 , wherein the first dielectric layer and the second dielectric layer have coefficients of thermal expansion (CTEs) in a range of 2 to 6 ppm/K.
26 . The device of claim 22 , further comprising one or more fourth dielectric layers placed under, on, or between the first dielectric layer and the second dielectric layer and having a composition, thickness, or microstructure different than the first dielectric layer and the second dielectric layer.
27 . The device of claim 16 , further comprising:
a board coupled to the package substrate.